Journals in DBLP

IEEE Trans. VLSI Syst.
2004, volume: 12, number: 7

1. Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha
   Multiple-symbol parallel decoding for variable length codes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:676-685 [Journal]
   
2. Sumio Morioka, Akashi Satoh
   A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:686-691 [Journal]
   
3. Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu
   Fitted Elmore delay: a simple and accurate interconnect delay model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:691-696 [Journal]
   
4. Ivan Blunno, Luciano Lavagno
   Designing an asynchronous microcontroller using Pipefitter. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:696-699 [Journal]
   
5. Yongchul Song, Beomsup Kim
   Quadrature direct digital frequency synthesizers using interpolation-based angle rotation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:701-710 [Journal]
   
6. Jian Liang, Andrew Laffely, S. Srinivasan, Russell Tessier
   An architecture and compiler for scalable on-chip communication. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:711-726 [Journal]
   
7. Arne Halaas, Børge Svingen, Magnar Nedland, Pål Sætrom, Ola R. Snøve Jr., Olaf René Birkeland
   A recursive MISD architecture for pattern matching. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:727-734 [Journal]
   
8. Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
   Placement constraints in floorplan design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:735-745 [Journal]
   
9. Yi Zhao, Sujit Dey, Li Chen
   Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:746-755 [Journal]
   
10. Sule Ozev, Alex Orailoglu
    Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:756-765 [Journal]
    
11. Keoncheol Shin, Taewhan Kim
    Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:766-775 [Journal]
    
12. Abhijit Jas, Bahram Pouya, Nur A. Touba
    Test data compression technique for embedded cores using virtual scan chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:775-781 [Journal]
    
13. Irith Pomeranz, Sudhakar M. Reddy
    Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:780-788 [Journal]