Journals in DBLP

IEEE Trans. VLSI Syst.
2004, volume: 12, number: 12

1. Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty
   SOC test planning using virtual test access architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1263-1276 [Journal]
   
2. Abhijit Jas, C. V. Krishna, Nur A. Touba
   Weighted pseudorandom hybrid BIST. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1277-1283 [Journal]
   
3. Miron Abramovici, Charles E. Stroud, John M. Emmert
   Online BIST and BIST-based diagnosis of FPGA logic blocks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1284-1294 [Journal]
   
4. Magdy A. El-Moursy, Eby G. Friedman
   Power characteristics of inductive interconnect. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1295-1306 [Journal]
   
5. Emad Gad, Michel S. Nakhla
   Efficient simulation of nonuniform transmission lines using integrated congruence transform. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1307-1320 [Journal]
   
6. A. Maheshwari, W. Burleson
   Differential current-sensing for on-chip interconnects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1321-1329 [Journal]
   
7. Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand
   Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1330-1347 [Journal]
   
8. Maged Ghoneima, Yehea I. Ismail
   Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1348-1359 [Journal]
   
9. Sanjukta Bhanja, N. Ranganathan
   Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1360-1370 [Journal]
   
10. William N. N. Hung, Xiaoyu Song, T. Kam, Lerong Cheng, Guowu Yang
    Routability checking for three-dimensional architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1371-1374 [Journal]
    
11. Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
    Bus-switch coding for reducing power dissipation in off-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1374-1377 [Journal]
    
12. Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Ron Hu
    A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1377-1381 [Journal]
    
13. Myungchul Yoon
    Sequence-switch coding for low-power data transmission. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1381-1385 [Journal]
    
14. Irith Pomeranz, Yervant Zorian
    Fault isolation for nonisolated blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1385-1388 [Journal]