Journals in DBLP

IEEE Trans. VLSI Syst.
2004, volume: 12, number: 3

1. Christian Piguet, Narayanan Vijaykrishnan
   Guest Editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:233-234 [Journal]
   
2. Amaury Nève, Helmut Schettler, Thomas Ludwig 0004, Denis Flandre
   Power-delay product minimization in high-performance 64-bit carry-select adders. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:235-244 [Journal]
   
3. Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar
   DCG: deterministic clock-gating for low-power microprocessor design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:245-254 [Journal]
   
4. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
   Memory energy minimization by data compression: algorithms, architectures and implementation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:255-268 [Journal]
   
5. Edgar G. Daylight, David Atienza, Arnout Vandecappelle, Francky Catthoor, José M. Mendías
   Memory-access-aware data structure transformations for embedded software with dynamic data accesses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:269-280 [Journal]
   
6. Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Ibrahim Kolcu
   Compiler-directed scratch pad memory optimization for embedded multiprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:281-287 [Journal]
   
7. Elias Ahmed, Jonathan Rose
   The effect of LUT and cluster size on deep-submicron FPGA performance and density. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:288-298 [Journal]
   
8. Atul Maheshwari, Wayne Burleson, Russell Tessier
   Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:299-311 [Journal]
   
9. Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, R. Anderson, J. R. Uribe
   Overview of a compiler for synthesizing MATLAB programs onto FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:312-324 [Journal]
   
10. Aristides Efthymiou, Jim D. Garside
    A CAM with mixed serial-parallel comparison for use in low energy caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:325-329 [Journal]