Journals in DBLP

IEEE Trans. VLSI Syst.
2005, volume: 13, number: 1

1. Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff
   The CSI multimedia architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:1-13 [Journal]
   
2. Emil Talpes, Diana Marculescu
   Execution cache-based microarchitecture for power-efficient superscalar processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:14-26 [Journal]
   
3. Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy
   A process-tolerant cache architecture for improved yield in nanoscale technologies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:27-38 [Journal]
   
4. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
   Optimum and heuristic synthesis of multiple word-length architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:39-57 [Journal]
   
5. Dongming Peng, Mi Lu
   Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:58-74 [Journal]
   
6. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
   Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:75-85 [Journal]
   
7. Lok-Kee Ting, Roger Woods, C. F. N. Cowan
   Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:86-95 [Journal]
   
8. Herman Schmit, Vikas Chandra
   Layout techniques for FPGA switch blocks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:96-105 [Journal]
   
9. Dongming Peng, Mi Lu
   On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:106-125 [Journal]
   
10. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
    A robust self-calibrating transmission scheme for on-chip networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:126-139 [Journal]
    
11. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Synchronization overhead in SOC compressed test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:140-152 [Journal]
    
12. Ahmad A. Hiasat
    VLSI implementation of new arithmetic residue to binary decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:153-158 [Journal]
    
13. Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu
    Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:158-162 [Journal]