Journals in DBLP
Peng Rong , Massoud Pedram An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:441-451 [Journal ] Massimo Alioto , Gaetano Palumbo , Massimo Poli Energy Consumption in RC Tree Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:452-461 [Journal ] A. Ye , J. Rose Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:462-473 [Journal ] Andy Yan , Steven J. E. Wilton Product-Term-Based Synthesizable Embedded Programmable Logic Cores. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:474-488 [Journal ] H.-Y. Hsu , J.-C. Yeo , A.-Y. Wu Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:489-500 [Journal ] Wei Huang , Shougata Ghosh , Sivakumar Velusamy , Karthik Sankaranarayanan , Kevin Skadron , Mircea R. Stan HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:501-513 [Journal ] Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee , Adit D. Singh Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:514-524 [Journal ] Yuan Xie , Wayne Wolf , Haris Lekatsas Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:525-536 [Journal ] Adam B. Kinsman , Scott Ollivierre , Nicola Nicolici Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:537-548 [Journal ] J.-J. Kim , K. Roy A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:549-552 [Journal ] Eric Wong , Jacob R. Minz , Sung Kyu Lim Multi-Objective Module Placement For 3-D System-On-Package. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:553-557 [Journal ]