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Journals in DBLP

IEEE Trans. VLSI Syst.
2006, volume: 14, number: 5

  1. Peng Rong, Massoud Pedram
    An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:441-451 [Journal]
  2. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Energy Consumption in RC Tree Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:452-461 [Journal]
  3. A. Ye, J. Rose
    Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:462-473 [Journal]
  4. Andy Yan, Steven J. E. Wilton
    Product-Term-Based Synthesizable Embedded Programmable Logic Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:474-488 [Journal]
  5. H.-Y. Hsu, J.-C. Yeo, A.-Y. Wu
    Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:489-500 [Journal]
  6. Wei Huang, Shougata Ghosh, Sivakumar Velusamy, Karthik Sankaranarayanan, Kevin Skadron, Mircea R. Stan
    HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:501-513 [Journal]
  7. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
    Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:514-524 [Journal]
  8. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:525-536 [Journal]
  9. Adam B. Kinsman, Scott Ollivierre, Nicola Nicolici
    Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:537-548 [Journal]
  10. J.-J. Kim, K. Roy
    A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:549-552 [Journal]
  11. Eric Wong, Jacob R. Minz, Sung Kyu Lim
    Multi-Objective Module Placement For 3-D System-On-Package. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:553-557 [Journal]
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