Journals in DBLP

IEEE Trans. VLSI Syst.
2006, volume: 14, number: 3

1. Mikhail Popovich, Eby G. Friedman
   Decoupling capacitors for multi-voltage power distribution systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:217-228 [Journal]
   
2. Woon Kang, Yong-Bin Kim, T. Doyle
   A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:229-240 [Journal]
   
3. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
   FABSYN: floorplan-aware bus architecture synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:241-253 [Journal]
   
4. Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
   A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:254-267 [Journal]
   
5. Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, T. Balsara
   A nonredundant ternary CAM circuit for network search engines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:268-278 [Journal]
   
6. Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis
   A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:279-291 [Journal]
   
7. Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
   Test infrastructure design for mixed-signal SOCs with wrapped analog cores. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:292-304 [Journal]
   
8. Erik Larsson, Hideo Fujiwara
   System-on-chip test scheduling with reconfigurable core wrappers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:305-309 [Journal]