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Journals in DBLP

IEEE Trans. VLSI Syst.
2006, volume: 14, number: 1

  1. Yajun Ran, Malgorzata Marek-Sadowska
    Designing via-configurable logic blocks for regular fabric. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:1-14 [Journal]
  2. Amine Bermak, Yat-Fong Yung
    A DPS array with programmable resolution and reconfigurable conversion time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:15-22 [Journal]
  3. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    SWAN: high-level simulation methodology for digital substrate noise generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:23-33 [Journal]
  4. Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu
    Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:34-42 [Journal]
  5. Y. Eslami, Ali Sheikholeslami, P. Glenn Gulak, S. Masui, K. Mukaida
    An area-efficient universal cryptography processor for smart cards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:43-56 [Journal]
  6. Ali Habibi, Sofiène Tahar
    Design and verification of SystemC transaction-level models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:57-68 [Journal]
  7. Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel
    Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:69-80 [Journal]
  8. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
    A power-driven multiplication instruction-set design method for ASIPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:81-85 [Journal]
  9. Yuming Zhu, L. Li, C. Chakrabarti
    Study of energy and performance of space-time decoding systems in concatenation with turbo decoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:86-90 [Journal]
  10. Sagar S. Sabade, D. M. H. Walker
    Estimation of fault-free leakage current using wafer-level spatial information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:91-94 [Journal]
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