Journals in DBLP

IEEE Trans. VLSI Syst.
2005, volume: 13, number: 9

1. Fei Sun, Tong Zhang
   Parallel high-throughput limited search trellis decoder VLSI design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1013-1022 [Journal]
   
2. Daehong Kim, Dongwan Shin, Kiyoung Choi
   Pipelining with common operands for power-efficient linear systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1023-1034 [Journal]
   
3. Yan Lin, Fei Li, Lei He
   Circuits and architectures for field programmable gate array with configurable supply voltage. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1035-1047 [Journal]
   
4. Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung
   Customizable elliptic curve cryptosystems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1048-1059 [Journal]
   
5. Xiaomeng Shi, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do, Erping Li
   Equivalent circuit model of on-wafer CMOS interconnects for RFICs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1060-1071 [Journal]
   
6. Yu Cao, Xiao-Dong Yang, Xuejue Huang, Dennis Sylvester
   Switch-factor based loop RLC modeling for efficient timing analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1072-1078 [Journal]
   
7. Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis
   Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1079-1086 [Journal]
   
8. Irith Pomeranz, Sudhakar M. Reddy
   Autoscan: a scan design without external scan inputs or outputs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1087-1095 [Journal]
   
9. Ashkan Ashrafi, Reza Adhami
   Comments on "A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula". [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1096-1098 [Journal]
   
10. X. P. Yu, Manh Anh Do, Lin Jia, Jianguo Ma, Kiat Seng Yeo
    Design of a low power wide-band high resolution programmable frequency divider. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1098-1103 [Journal]
    
11. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1103-1107 [Journal]