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Journals in DBLP

IEEE Trans. VLSI Syst.
2005, volume: 13, number: 2

  1. Brian Moore, Martin Margala, Christopher J. Backhouse
    Design of wireless on-wafer submicron characterization system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:169-180 [Journal]
  2. Marko Kosunen, Jouko Vankka, Mikko Waltari, Kari Halonen
    A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:181-190 [Journal]
  3. Francesco Centurelli, A. Golfarelli, J. Guinea, L. Masini, D. Morigi, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
    A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:191-200 [Journal]
  4. Liming Xiu, Zhihong You
    A "Flying-Adder" frequency synthesis architecture of reducing VCO stages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:201-210 [Journal]
  5. V. Raghunathan, C. L. Pereira, M. B. Srivastava, R. K. Gupta
    Energy-aware wireless systems with adaptive power-fidelity tradeoffs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:211-225 [Journal]
  6. P. Chowdhury, C. Chakrabarti
    Static task-scheduling algorithms for battery-powered DVS systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:226-237 [Journal]
  7. W. W. Bachmann, S. A. Huss
    Efficient algorithms for multilevel power estimation of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:238-254 [Journal]
  8. Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
    A micropower low-voltage multiplier with reduced spurious switching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:255-265 [Journal]
  9. Neil Burgess
    Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:266-277 [Journal]
  10. Soha Hassoun, Murali Kudlugi, Duaine Pryor, Charles Selvidge
    A transaction-based unified architecture for simulation and emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:278-287 [Journal]
  11. Jai-Ming Lin, Yao-Wen Chang
    TCG: A transitive closure graph-based representation for general floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:288-292 [Journal]
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