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Journals in DBLP

IEEE Trans. VLSI Syst.
2004, volume: 12, number: 6

  1. Jennifer L. Wong, Gang Qu, Miodrag Potkonjak
    Power minimization in QoS sensitive systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:553-561 [Journal]
  2. Saraju P. Mohanty, Nagarajan Ranganathan
    A framework for energy and transient power reduction during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:562-572 [Journal]
  3. Noureddine Chabini, Wayne Wolf
    Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:573-589 [Journal]
  4. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input space adaptive design: a high-level methodology for optimizing energy and performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:590-602 [Journal]
  5. Mahmoud Meribout, Masato Motomura
    Efficient metrics and high-level synthesis for dynamically reconfigurable logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:603-621 [Journal]
  6. Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
    Pel reconstruction on FPGA-augmented TriMedia. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:622-635 [Journal]
  7. J. V. Deodhar, Spyros Tragoudas
    Implicit deductive fault simulation for complex delay fault models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:636-641 [Journal]
  8. Jun Jin Kong, Keshab K. Parhi
    Low-latency architectures for high-throughput rate Viterbi decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:642-651 [Journal]
  9. R. Singh, N. Bhat
    An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:652-657 [Journal]
  10. Imed Ben Dhaou, Hannu Tenhunen
    Efficient library characterization for high-level power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:657-661 [Journal]
  11. A. Valentian, O. Thomas, Andrei Vladimirescu, Amara Amara
    Modeling subthreshold SOI logic for static timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:662-669 [Journal]
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