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Journals in DBLP

IEEE Trans. VLSI Syst.
2004, volume: 12, number: 8

  1. Paul Pop, Petru Eles, Zebo Peng, Traian Pop
    Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:793-811 [Journal]
  2. Peter Petrov, Alex Orailoglu
    Low-power instruction bus encoding for embedded processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:812-826 [Journal]
  3. Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
    Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:827-836 [Journal]
  4. Naehyuck Chang, Inseok Choi, Hojun Shim
    DLS: dynamic backlight luminance scaling of liquid crystal display. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:837-846 [Journal]
  5. Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar
    Asynchronous gate-diffusion-input (GDI) circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:847-856 [Journal]
  6. Tiberiu Chelcea, Steven M. Nowick
    Robust interfaces for mixed-timing systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:857-873 [Journal]
  7. Shinn-Ying Ho, Shinn-Jang Ho, Yi-Kuang Lin, W. C.-C. Chu
    An orthogonal simulated annealing algorithm for large floorplanning problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:874-877 [Journal]
  8. Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards
    A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:876-880 [Journal]
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