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Journals in DBLP

IEEE Trans. VLSI Syst.
2004, volume: 12, number: 1

  1. N. Ranganathan
    Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:1-11 [Journal]
  2. Baris Taskin, Ivan S. Kourtev
    Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:12-27 [Journal]
  3. Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
    Timing modeling and optimization under the transmission line model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:28-41 [Journal]
  4. Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh
    Timing driven gate duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:42-51 [Journal]
  5. R. Galli, Alexandre F. Tenca
    A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:52-66 [Journal]
  6. Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman
    Substrate coupling in digital circuits in mixed-signal smart-power systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:67-78 [Journal]
  7. Antonio H. Chan, Gordon W. Roberts
    A jitter characterization system using a component-invariant Vernier delay line. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:79-95 [Journal]
  8. Tajana Simunic, Stephen P. Boyd, Peter W. Glynn
    Managing power consumption in networks on chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:96-107 [Journal]
  9. Girish Varatkar, Radu Marculescu
    On-chip traffic modeling and synthesis for MPEG-2 video applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:108-119 [Journal]
  10. Roman L. Lysecky, Susan Cotterell, Frank Vahid
    A fast on-chip profiler memory using a pipelined binary tree. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:120-122 [Journal]
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