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Journals in DBLP

IEEE Trans. VLSI Syst.
2005, volume: 13, number: 4

  1. Xinmiao Zhang, Keshab K. Parhi
    Fast factorization architecture in soft-decision Reed-Solomon decoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:413-426 [Journal]
  2. Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar
    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:427-438 [Journal]
  3. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen
    VLSI architectural design tradeoffs for sliding-window log-MAP decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:439-447 [Journal]
  4. Sunan Tugsinavisut, Youpyo Hong, Daewook Kim, Kyeounsoo Kim, Peter A. Beerel
    Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:448-461 [Journal]
  5. M. E. Litvin, S. Mourad
    Self-reset logic for fast arithmetic applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:462-475 [Journal]
  6. Chang Hoon Kim, Chun Pyo Hong, Soonhak Kwon
    A digit-serial multiplier for finite field GF(2/sup m/). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:476-483 [Journal]
  7. Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson
    A reconfigurable, power-efficient adaptive Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:484-488 [Journal]
  8. Keshab K. Parhi
    Design of multigigabit multiplexer-loop-based decision feedback equalizers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:489-493 [Journal]
  9. M. Tiwari, Yuming Zhu, C. Chakrabarti
    Memory sub-banking scheme for high throughput MAP-based SISO decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:494-498 [Journal]
  10. S. Parameswaran, J. Henkel
    Instruction code mapping for performance increase and energy reduction in embedded computer systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:498-502 [Journal]
  11. Swarup Bhunia, Kaushik Roy
    A novel wavelet transform-based transient current analysis for fault detection and localization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:503-507 [Journal]
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