Journals in DBLP

IEEE Trans. VLSI Syst.
2005, volume: 13, number: 11

1. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
   Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1213-1224 [Journal]
   
2. Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
   Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1225-1238 [Journal]
   
3. Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner
   The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1239-1252 [Journal]
   
4. Robert B. Staszewski, Roman Staszewski, John L. Wallberg, T. Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, K. Maggio, Poras T. Balsara
   SoC with an integrated DSP and a 2.4-GHz RF transmitter. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1253-1265 [Journal]
   
5. Antonio G. M. Strollo, Davide De Caro, E. Napoli, Nicola Petra
   A novel high-speed sense-amplifier-based flip-flop. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1266-1274 [Journal]
   
6. Qiang Xu, Nicola Nicolici
   Modular and rapid testing of SOCs with unwrapped logic blocks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1275-1285 [Journal]
   
7. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
   Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1286-1295 [Journal]
   
8. Bhaskar Chatterjee, Manoj Sachdev
   Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1296-1304 [Journal]
   
9. Ju-wook Jang, S. B. Choi, Viktor K. Prasanna
   Energy- and time-efficient matrix multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1305-1319 [Journal]
   
10. Peter Hallschmid, Steven J. E. Wilton
    Routing architecture optimizations for high-density embedded programmable IP cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1320-1324 [Journal]
    
11. Weiping Liao, Joseph M. Basile, Lei He
    Microarchitecture-level leakage reduction with data retention. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1324-1328 [Journal]