The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. VLSI Syst.
2004, volume: 12, number: 9

  1. Rouwaida Kanj, Elyse Rosenbaum
    Critical evaluation of SOI design guidelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:885-894 [Journal]
  2. Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Chih-Chen Li, Ron Hu
    A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:895-900 [Journal]
  3. Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu
    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:901-909 [Journal]
  4. Li Ding 0002, Pinaki Mazumder
    On circuit techniques to improve noise immunity of CMOS dynamic logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:910-925 [Journal]
  5. Sarvesh H. Kulkarni, Dennis Sylvester
    High performance level conversion for dual VDD design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:926-936 [Journal]
  6. Changbo Long, Lei He
    Distributed sleep transistor network for power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:937-946 [Journal]
  7. L. T. Clark, M. Morrow, W. Brown
    Reverse-body bias and supply collapse for low effective standby power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:947-956 [Journal]
  8. Xinmiao Zhang, Keshab K. Parhi
    High-speed VLSI architectures for the AES algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:957-967 [Journal]
  9. J. Kaza, C. Chakrabarti
    Design and implementation of low-energy turbo decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:968-977 [Journal]
  10. Mathew A. Sacker, Andrew D. Brown, Andrew J. Rushton, Peter R. Wilson
    A behavioral synthesis system for asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:978-994 [Journal]
  11. Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo
    Variable precision arithmetic circuits for FPGA-based multimedia processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:995-999 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002