Journals in DBLP

IEEE Trans. VLSI Syst.
2005, volume: 13, number: 12

1. Shrirang K. Karandikar, Sachin S. Sapatnekar
   Fast comparisons of circuit implementations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1329-1339 [Journal]
   
2. Chuan Lin, Hai Zhou
   Wire retiming as fixpoint computation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1340-1348 [Journal]
   
3. Sandy Irani, G. Singh, Sandeep K. Shukla, Rajesh K. Gupta
   An overview of the competitive and adversarial approaches to designing dynamic power management strategies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1349-1361 [Journal]
   
4. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
   Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1362-1375 [Journal]
   
5. Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester
   Bus encoding for total power reduction using a leakage-aware buffer configuration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1376-1383 [Journal]
   
6. Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
   Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1384-1393 [Journal]
   
7. Andreas Dandalis, Viktor K. Prasanna
   Configuration compression for FPGA-based embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1394-1398 [Journal]
   
8. Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh
   A multiparameter implantable microstimulator SOC. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1399-1402 [Journal]