Journals in DBLP

IEEE Trans. VLSI Syst.
2005, volume: 13, number: 5

1. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
   Memory binding for performance optimization of control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:513-524 [Journal]
   
2. Nattawut Thepayasuwan, Alex Doboli
   Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:525-538 [Journal]
   
3. Sungchan Kim, Chaeseok Im, Soonhoi Ha
   Schedule-aware performance estimation of communication architecture for efficient design space exploration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:539-552 [Journal]
   
4. Fred Ma, John P. Knight, Calvin Plett
   Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:553-563 [Journal]
   
5. Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar
   Combined circuit and architectural level variable supply-voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:564-576 [Journal]
   
6. Nikola Nedovic, Vojin G. Oklobdzija
   Dual-edge triggered storage elements and clocking strategy for low-power systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:577-590 [Journal]
   
7. Emil Talpes, Diana Marculescu
   Toward a multiple clock/voltage island design style for power-aware processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:591-603 [Journal]
   
8. Ted H. Szymanski, Honglin Wu, Amir Gourgy
   Power complexity of multiplexer-based optoelectronic crossbar switches. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:604-617 [Journal]
   
9. Amin Q. Safarian, Ahmad Yazdi, Payam Heydari
   Design and analysis of an ultrawide-band distributed CMOS mixer. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:618-629 [Journal]
   
10. Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
    A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:630-638 [Journal]