Journals in DBLP

IEEE Trans. VLSI Syst.
2006, volume: 14, number: 9

1. Ming-Bo Lin, Jang-Feng Lee, Gene Eu Jan
   A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:925-936 [Journal]
   
2. Zhongfeng Wang, Jun Ma
   High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:937-950 [Journal]
   
3. Hooman Nikmehr, Braden Phillips, Cheng-Chew Lim
   Fast Decimal Floating-Point Division. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:951-961 [Journal]
   
4. Minghua Shi, Amine Bermak
   An Efficient Digital VLSI Implementation of Gaussian Mixture Models-Based Classifier. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:962-974 [Journal]
   
5. Recep O. Ozdag, Peter A. Beerel
   An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:975-985 [Journal]
   
6. Jason Cong, Guoling Han, Zhiru Zhang
   Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:986-997 [Journal]
   
7. Yajun Ran, Malgorzata Marek-Sadowska
   Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:998-1009 [Journal]
   
8. K. N. Vikram, V. Vasudevan
   Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:1010-1023 [Journal]
   
9. Mehdi Baradaran Tahoori
   Application-Dependent Testing of FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:1024-1033 [Journal]
   
10. Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi
    Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:1034-1039 [Journal]
    
11. Madhavi Gopal Valluri, Lizy Kurian John, Heather Hanson
    Hybrid-Scheduling for Reduced Energy Consumption in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:1039-1043 [Journal]
    
12. Ilya Obridko, Ran Ginosar
    Minimal Energy Asynchronous Dynamic Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:1043-1047 [Journal]