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Journals in DBLP

IEEE Trans. VLSI Syst.
2006, volume: 14, number: 7

  1. Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Damien Lyonnard, Olivier Benny, Bruno Lavigueur, David Lo, Giovanni Beltrame, V. Gagne, Gabriela Nicolescu
    Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:667-680 [Journal]
  2. Sungchan Kim, Soonhoi Ha
    Efficient exploration of bus-based system-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:681-692 [Journal]
  3. Ümit Y. Ogras, Radu Marculescu
    "It's a small world after all": NoC performance optimization via long-range link insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:693-706 [Journal]
  4. Xinping Zhu, Wei Qin, Sharad Malik
    Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:707-716 [Journal]
  5. Linwei Niu, Gang Quan
    Energy minimization for real-time systems with (m, k)-guarantee. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:717-729 [Journal]
  6. Juanjo Noguera, Rosa M. Badia
    System-level power-performance tradeoffs for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:730-739 [Journal]
  7. Catherine H. Gebotys
    A table masking countermeasure for low-energy secure embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:740-753 [Journal]
  8. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:754-762 [Journal]
  9. Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
    Extraction error modeling and automated model debugging in high-performance custom designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:763-776 [Journal]
  10. Denis Deschacht
    DSM interconnects: importance of inductance effects and corresponding range of length. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:777-779 [Journal]
  11. Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang
    Instruction buffering for nested loops in low-power design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:780-784 [Journal]
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