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Journals in DBLP

IEEE Trans. VLSI Syst.
2006, volume: 14, number: 8

  1. Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau
    Retargetable pipeline hazard detection for partially bypassed processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:791-801 [Journal]
  2. Manish Verma, Peter Marwedel
    Overlay techniques for scratchpad memories in low power embedded processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:802-815 [Journal]
  3. Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
    Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:816-829 [Journal]
  4. Mohammad Ali Ghodrat, Tony Givargis, Alexandru Nicolau
    Expression equivalence checking using interval analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:830-842 [Journal]
  5. Soheil Ghiasi, Po-Kuan Huang, Roozbeh Jafari
    Probabilistic delay budget assignment for synthesis of soft real-time applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:843-853 [Journal]
  6. Stephen A. Edwards, Olivier Tardieu
    SHIM: a deterministic model for heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:854-867 [Journal]
  7. JoAnn M. Paul, Donald E. Thomas, Alex Bobrek
    Scenario-oriented design for single-chip heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:868-880 [Journal]
  8. Lihong Zhang, Ulrich Kleine, Yingtao Jiang
    An automated design tool for analog layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:881-894 [Journal]
  9. V. Chaudhary, Lawrence T. Clark
    Low-power high-performance nand match line content addressable memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:895-905 [Journal]
  10. I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson
    Placement for large-scale floating-gate field-programable analog arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:906-910 [Journal]
  11. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Virtual memory window for application-specific reconfigurable coprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:910-915 [Journal]
  12. Jae H. Baek, Myung Hoon Sunwoo
    New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:915-920 [Journal]
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