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Journals in DBLP

Microprocessors and Microsystems
2006, volume: 30, number: 7

  1. T. K. Priya, P. Rajesh Kumar, K. Sridharan
    A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:7, pp:413-424 [Journal]
  2. Chin-Hsiung Wu, Shi-Jinn Horng, Yuh-Rau Wang, Horng-Ren Tsai
    Optimal geometric algorithms for digitized images on arrays with reconfigurable optical buses. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:7, pp:425-434 [Journal]
  3. Eva M. Ortigosa, Antonio Cañas, Eduardo Ros, Pilar Martínez Ortigosa, Sonia Mota, Javier Díaz
    Hardware description of multi-layer perceptrons with different abstraction levels. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:7, pp:435-444 [Journal]
  4. Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones
    Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:7, pp:445-456 [Journal]
  5. Yehuda Sadeh Weinraub, Shlomo Weiss
    Power-aware out-of-order issue logic in high-performance microprocessors. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:7, pp:457-467 [Journal]
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