Journals in DBLP
T. K. Priya , P. Rajesh Kumar , K. Sridharan A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2006, v:30, n:7, pp:413-424 [Journal ] Chin-Hsiung Wu , Shi-Jinn Horng , Yuh-Rau Wang , Horng-Ren Tsai Optimal geometric algorithms for digitized images on arrays with reconfigurable optical buses. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2006, v:30, n:7, pp:425-434 [Journal ] Eva M. Ortigosa , Antonio Cañas , Eduardo Ros , Pilar Martínez Ortigosa , Sonia Mota , Javier Díaz Hardware description of multi-layer perceptrons with different abstraction levels. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2006, v:30, n:7, pp:435-444 [Journal ] Joshua M. Lucas , Raymond Hoare , Ivan S. Kourtev , Alex K. Jones Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2006, v:30, n:7, pp:445-456 [Journal ] Yehuda Sadeh Weinraub , Shlomo Weiss Power-aware out-of-order issue logic in high-performance microprocessors. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2006, v:30, n:7, pp:457-467 [Journal ]