Journals in DBLP

Microprocessors and Microsystems
2006, volume: 30, number: 5

1. Kai-Feng Wang, Zhenzhou Ji, Ming-Zeng Hu
   Boosting SMT trace processors performance with data cache misssensitive thread scheduling mechanism. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2006, v:30, n:5, pp:225-233 [Journal]
   
2. W. Kurdthongmee
   The hardware-based implementation of the colour palette generation stage of a colour image quantization algorithm. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2006, v:30, n:5, pp:234-249 [Journal]
   
3. Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata
   SAD computation based on online arithmetic for motion estimation. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2006, v:30, n:5, pp:250-258 [Journal]
   
4. Yongqiang Ye, Danwei Wang
   Implementation of ILC batch update using a robotic experimental setup. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2006, v:30, n:5, pp:259-267 [Journal]
   
5. Cheol Hong Kim, Sung Woo Chung, Chu Shik Jhon
   PP-cache: A partitioned power-aware instruction cache architecture. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2006, v:30, n:5, pp:268-279 [Journal]