Journals in DBLP

Microprocessors and Microsystems
2005, volume: 29, number: 8-9

1. Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido
   Recent advances in computer vision and image processing using reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:359-362 [Journal]
   
2. Manjunath Gangadhar, Dinesh Bhatia
   FPGA based EBCOT architecture for JPEG 2000. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:363-373 [Journal]
   
3. Jesús Lázaro, Jagoba Arias, José Luis Martín, Carlos Cuadrado, Armando Astarloa
   Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:375-380 [Journal]
   
4. Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo
   A high-performance fully reconfigurable FPGA-based 2D convolution processor. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:381-391 [Journal]
   
5. Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses
   The rapid prototyping experience of an H.263 video coder onto FPGA. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:393-404 [Journal]
   
6. N. Sudha
   A pipelined array architecture for Euclidean distance transformation and its FPGA implementation. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:405-410 [Journal]
   
7. Ana Toledo Moreo, Pedro Navarro Lorente, F. Soto Valles, Juan Suardíaz Muro, Carlos Fernández Andrés
   Experiences on developing computer vision hardware algorithms using Xilinx system generator. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:411-419 [Journal]