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Journals in DBLP

Microprocessors and Microsystems
2004, volume: 28, number: 5-6

  1. Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido
    Guest editors' introduction - Special issue on FPGAs: applications and designs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:193-195 [Journal]
  2. Valery Sklyarov
    FPGA-based implementation of recursive algorithms. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:197-211 [Journal]
  3. Tom Van Court, Martin C. Herbordt, Richard J. Barton
    Case study of a functional genomics application for an FPGA-based coprocessor. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:213-222 [Journal]
  4. Aristides Nikologiannis, Ioannis Papaefstathiou, George Kornaros, Christopher Kachris
    An FPGA-based queue management system for high speed networking devices. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:223-236 [Journal]
  5. Paul Berube, Mike MacGregor, José Nelson Amaral
    FPGA implementation and experimental evaluation of a multizone network cache. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:237-252 [Journal]
  6. Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici
    An FPGA implementation of a GF(p) ALU for encryption processors. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:253-260 [Journal]
  7. F. A. Karnapi, W. S. Gan, Y. K. Chong
    FPGA implementation of parametric loudspeaker system. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:261-272 [Journal]
  8. Leonardo Maria Reyneri
    A Simulink-based hybrid codesign tool for rapid prototyping of FPGA's in signal processing systems. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:273-289 [Journal]
  9. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
    A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:291-301 [Journal]
  10. José Albaladejo, David de Andrés, Lenin Lemus, Joaquim Salvi
    Codesign methodology for computer vision applications. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:303-316 [Journal]
  11. Alireza Ejlali, Seyed Ghassem Miremadi
    FPGA-based fault injection into switch-level models. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:317-327 [Journal]
  12. Francisco Rodríguez-Henríquez, Nazar A. Saqib, Arturo Díaz-Pérez
    A fast parallel implementation of elliptic curve point multiplication over GF(2m). [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:329-339 [Journal]
  13. Young-Su Kwon, Chong-Min Kyung
    Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:341-350 [Journal]
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