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Journals in DBLP

Microprocessors and Microsystems
2007, volume: 31, number: 2

  1. J. Morris Chang, C. Dan Lo
    FPGA-based reconfigurable computing II. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:- [Journal]
  2. J. Castillo, P. Huerta, J. I. Martínez
    Secure IP downloading for SRAM FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:77-86 [Journal]
  3. S. W. Alexander, E. Pfann, R. W. Stewart
    An improved algorithm for assessing the overall quantisation error in FPGA based CORDIC systems computing a vector magnitude. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:87-93 [Journal]
  4. Ming-Haw Jing, Zih-Heng Chen, Jian-Hong Chen, Yan-Haw Chen
    Reconfigurable system for high-speed and diversified AES using FPGA. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:94-102 [Journal]
  5. Chuan He, Guan Qin, Mi Lu, Wei Zhao
    Optimized high-order finite difference wave equations modeling on reconfigurable computing platform. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:103-115 [Journal]
  6. Alex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle
    An automated, FPGA-based reconfigurable, low-power RFID tag. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:116-134 [Journal]
  7. Tom Van Court, Martin C. Herbordt
    Families of FPGA-based accelerators for approximate string matching. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:135-145 [Journal]
  8. Richard B. Kujoth, Chi-Wei Wang, Jeffrey J. Cook, Derek B. Gottlieb, Nicholas P. Carter
    A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:146-159 [Journal]
  9. Dimitrios K. Iakovidis, Dimitrios E. Maroulis, Dimitris G. Bariamis
    FPGA architecture for fast parallel computation of co-occurrence matrices. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:160-165 [Journal]
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