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Microelectronics Reliability
2001, volume: 41, number: 9-10

  1. Lifeng Wu, Zhihong Liu
    Full-Chip Reliability Simulation for VDSM Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1273-1278 [Journal]
  2. Per-Olof Fägerholt
    Reliability improvements in passive components. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1279-1288 [Journal]
  3. A. Muehlhoff
    An Extrapolation Model for Lifetime Prediction for Off-State - Degradation of MOS-FETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1289-1293 [Journal]
  4. F. Monsieur, E. Vincent, D. Roy, S. Bruyère, G. Pananakakis, G. Ghibaudo
    Determination of Dielectric Breakdown Weibull Distribution Parameters Confidence Bounds for Accurate Ultrathin Oxide Reliability Predictions. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1295-1300 [Journal]
  5. Young Pil Kim, Beom Jun Jin, Young Wook Park, Joo Tae Moon, Sang U. Kim
    Analysis of retention tail distribution induced by scaled shallow trench isolation for high densityDRAMs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1301-1305 [Journal]
  6. N. Revil, X. Garros
    Hot-Carrier Reliability for Si and SiGe HBTs: Aging Procedure, Extrapolation Model Limitations and Applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1307-1312 [Journal]
  7. A. Bravaix, D. Goguenheim, N. Revil, E. Vincent
    Injection Mechanisms and Lifetime Prediction with the Substrate Voltage in 0.15mum Channel-Length N-MOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1313-1318 [Journal]
  8. H. Puchner, Y.-C. Liu, W. Kong, F. Duan, R. Castagnetti
    Substrate Engineering to Improve Soft-Error-Rate Immunity for SRAM Technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1319-1324 [Journal]
  9. Hamid Toutah, Jean-François Llibre, Boubekeur Tala-Ighil, Taieb Mohammed-Brahim, Youri Helen, G. Gautier, Olivier Bonnaud
    Improved Stability of Large Area Excimer Laser Crstallised Polysilicon Thin Film Transistors under DC and AC Operating. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1325-1329 [Journal]
  10. Yannick Rey-Tauriac, M. Taurin, Olivier Bonnaud
    Wafer Level Accelerated test for ionic contamination control on VDMOS transistors in Bipolar/CMOS/DMOS. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1331-1334 [Journal]
  11. Xavier Gagnard, Yannick Rey-Tauriac, Olivier Bonnaud
    Polysilicon oxide quality optimization at Wafer level of a Bipolar/CMOS/DMOS technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1335-1340 [Journal]
  12. M. Nakabayashi, H. Ohyama, E. Simoen, M. Ikegami, C. Claeys, K. Kobayashi, M. Yoneoka, K. Miyahara
    Reliability of polycrystalline silicon thin film resistors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1341-1346 [Journal]
  13. A. Ghetti, M. Alam, J. Bude
    Anode hole generation mechanisms. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1347-1354 [Journal]
  14. D. Zander, F. Saigné, A. Meinertzhagen
    Creation and thermal annealing of interface states induced by uniform or localized injection in 2.3nm thick oxides. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1355-1360 [Journal]
  15. M. Fadlallah, A. Szewczyk, C. Giannakopoulos, B. Cretu, F. Monsieur, T. Devoivre, J. Jomaah, G. Ghibaudo
    Low frequency noise and reliability properties pf 0.12 mum CMOS devices with Ta2O5 as gate dielectrics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1361-1366 [Journal]
  16. S. Bruyère, F. Monsieur, D. Roy, E. Vincent, G. Ghibaudo
    Failures in ultrathin oxides: Stored energy or carrier energy driven? [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1367-1372 [Journal]
  17. Ninoslav Stojadinovic, I. Manic, S. Djoric-Veljkovic, V. Davidovic, S. Golubovic, S. Dimitrijev
    Mechanisms of positive gate bias stress induced instabilities in power VDMOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1373-1378 [Journal]
  18. K. Gonf, H. G. Feng, R. Y. Zhan, A. Z. Wang
    ESD-Induced Circuit Performance Degradation in RFICs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1379-1383 [Journal]
  19. Martin Litzenberger, R. Pichler, Scrgey Bychikhin, Dionyz Pogany, E. Gornik, K. Esmark, Harald Gossner
    Effect of pulse risetime on trigger homogeneity in single finger grounded gate nMOSFET electrostatic discharge protection devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1385-1390 [Journal]
  20. N. Tosic Golo, S. van der Wal, Fred G. Kuper, Ton J. Mouthaan
    The time-voltage trade-off for ESD damage threshold in amorphous silicon hydrogenated thin-film transistors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1391-1396 [Journal]
  21. Joachim C. Reiner, Thomas Keller
    Relevance of contact reliability in HBM-ESD test equipment. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1397-1401 [Journal]
  22. Jan Ackaert, Z. Wang, Eddy De Backer, P. Colson, Peter Coppens
    Non Contact Surface Potential Measurements for Charging Reduction During Manufacturing of Metal-Insulator-Metal Capacitors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1403-1407 [Journal]
  23. S. Yokogawa, N. Okada, Y. Kakuhara, H. Takizawa
    Electromigration Performance of Multi-level Damascene Copper Interconnects. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1409-1416 [Journal]
  24. F. Dieudonné, F. Daugé, J. Jomaah, C. Raynaud, F. Balestra
    An overview of hot-carrier induced degradation in 0.25 mum Partially and Fully Depleted SOI N-MOSFET's. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1417-1420 [Journal]
  25. F. Lime, G. Ghibaudo, G. Guégan
    Stress induced leakage current at low field in ultra thin oxides. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1421-1425 [Journal]
  26. G. Chen, M. F. Li, Y. Jin
    Electric passivation of interface traps at drain junction space charge region in p-MOS transistors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1427-1431 [Journal]
  27. A. Guilhaume, P. Galy, J. P. Chante, B. Foucher, F. Blanc
    Simulation and experimental comparison of GGNMOS and LVTSCR protection cells under ElectroStatic Discharges. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1433-1437 [Journal]
  28. K. Croes, R. Dreesen, J. Manca, Ward De Ceuninck, Luc De Schepper, L. Tielemans, P. van Der Wel
    High-resolution in-situ of gold electromigration: test time reduction. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1439-1442 [Journal]
  29. H. Ohyama, M. Nakabayashi, E. Simoen, C. Claeys, T. Tanaka, T. Hirao, S. Onada, K. Kobayashi
    Radiation damages of polycrystalline silicon films and npn Si transistors by high-energy particle irradiation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1443-1448 [Journal]
  30. Bernd Ebersberger, Alexander Olbrich, Christian Boit
    Application of Scanning Probe Microscopy techniques in Semiconductor Failure Analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1449-1458 [Journal]
  31. H. Yabuhara, Mauro Ciappa, Wolfgang Fichtner
    Diamond-Coated Cantilevers for Scanning Capacitance Microscopy Applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1459-1463 [Journal]
  32. J. C. Tsang, Massimo V. Fischetti
    Why hot carrier emission based timing probes will work for 50 nm, 1V CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1465-1470 [Journal]
  33. D. Lewis, V. Pouget, T. Beauchêne, H. Lapuyade, P. Fouillat, A. Touboul, Felix Beaudoin, Philippe Perdu
    Front Side and Backside OBIT Mappings applied to Single Event Transient Testing. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1471-1476 [Journal]
  34. Felix Beaudoin, X. Chauffleur, J. P. Fradin, Philippe Perdu, Romain Desplats, D. Lewis
    Modeling Thermal Laser Stimulation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1477-1482 [Journal]
  35. C.-C. Tsao, Q. S. Wang, P. Bouchet, P. Sudraud
    Coaxial Ion-Photon System. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1483-1488 [Journal]
  36. Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka
    Development of an EB/FIB Integrated Test System. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1489-1494 [Journal]
  37. Romain Desplats, Philippe Perdu, Felix Beaudoin
    A New Versatile Testing Interface for Failure Analysis in Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1495-1499 [Journal]
  38. Scrgey Bychikhin, Martin Litzenberger, R. Pichler, Dionyz Pogany, E. Gornik, G. Groos, M. Stecher
    Thermal and free carrier laser interferometric mapping and failure analysis of anti-serial smart power ESD protection structures. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1501-1506 [Journal]
  39. Norman Goldblatt, Martin Leibowitz, William Lo
    Unique and Practical IC Timing Analysis Tool Utilizing Intrinsic Photon Emission. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1507-1512 [Journal]
  40. V. Pouget, H. Lapuyade, P. Fouillat, D. Lewis, S. Buchner
    Theoretical Investigation of an Equivalent Laser LET. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1513-1518 [Journal]
  41. M. Zmeck, J. Phang, A. Bettiol, T. Osipowicz, F. Watt, L. Balk, F.-J. Niedernostheide, H.-J. Schulze, E. Falck, R. Barthelmess
    Analysis of high-power devices using proton beam induced charge microscopy. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1519-1524 [Journal]
  42. Kazuko Ikeda
    Evaluation method for the control of process induced defect in deep sub-micron device fabrication. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1525-1533 [Journal]
  43. M. Leicht, G. Fritzer, B. Basnar, S. Golka, J. Smoliner
    A reliable course of Scanning Capacitance Microscopy analysis applied for 2D-Dopant Profilings of Power MOSFET Devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1535-1537 [Journal]
  44. Romain Desplats, Felix Beaudoin, Philippe Perdu, P. Poirier, D. Trémouilles, M. Bafleur, D. Lewis
    Backside Localization of Current Leakage Faults Using Thermal Laser Stimulation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1539-1544 [Journal]
  45. T. Lundquist, E. Delenia, J. Harroun, E. LeRoy, C.-C. Tsao
    Ultra-Thinning of C4 Integrated Circuits for Backside Analysis during First Silicon Debug. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1545-1549 [Journal]
  46. Jon C. Lee, David Su, J. H. Chuang
    A Novel Application of the FIB Lift-out Technique for 3-D TEM Analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1551-1556 [Journal]
  47. Felix Beaudoin, Philippe Perdu, Romain Desplats, S. Rigo, D. Lewis
    Silicon Thinning and Polishing on Packaged Devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1557-1561 [Journal]
  48. A. Scavennec
    Introduction of InP high speed electronics into optical fiber transmission systems and current technological limits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1563-1566 [Journal]
  49. Cezary Sydlo, Bastian Mottet, Husin Ganis, Hans L. Hartnagel, Viktor Krozer, S. L. Delage, Simone Cassette, Eric Chartier, D. Floriot, Steven Bland
    Defect detection and modelling using pulsed electrical stress for reliability investigations of InGaP HBT. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1567-1571 [Journal]
  50. B. Lambert, N. Malbert, N. Labat, F. Verdier, A. Touboul, P. Huguet, R. Bonnet, G. Pataut
    Evolution of LF noise in Power PHEMT's submitted to RF and DC Step Stresses. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1573-1578 [Journal]
  51. Gaudenzio Meneghesso, Gaudenzio Chini, Enrico Zanoni
    Long Term Stability of InGaAs/AlInAs/GaAs Methamorphic HEMTs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1579-1584 [Journal]
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