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Microelectronics Reliability
2001, volume: 41, number: 11

  1. Markus P. J. Mergens
    Foreword - On-Chip ESD. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1737- [Journal]
  2. Koen G. Verhaege, Christian C. Russ
    Novel fully silicided ballasting and MFT design techniques for ESD protection in advanced deep sub-micron CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1739-1749 [Journal]
  3. James W. Miller, Michael G. Khazhinsky, James C. Weldon
    Layout and bias options for maximizing Vt1 in cascoded NMOS output buffers. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1751-1760 [Journal]
  4. K. Esmark, Wolfgang Stadler, M. Wendel, Harald Gossner, X. Guggenmos, Wolfgang Fichtner
    Advanced 2D/3D ESD device simulation - a powerful tool already used in a pre-Si phase. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1761-1770 [Journal]
  5. Jie Wu, Patrick Juliano, Elyse Rosenbaum
    Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1771-1779 [Journal]
  6. Yu Wang, Patrick Juliano, Sopan Joshi, Elyse Rosenbaum
    Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1781-1787 [Journal]
  7. Leo G. Henry, Mark A. Kelly, Tom Diep, Jon Barth
    The importance of standardizing CDM ESD test head parameters to obtain data correlation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1789-1800 [Journal]
  8. Franco Stellari, F. Zappa, S. Cova, L. Vendrame
    Tools for contactless testing and simulation of CMOS circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1801-1808 [Journal]
  9. Fernanda Irrera
    Electrical degradation and recovery of dielectrics in n++-poly-Si/SiOx/SiO2/p-sub structures designed for application in low-voltage non-volatile memories. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1809-1813 [Journal]
  10. F. A. Stam, E. Davitt
    Effects of thermomechanical cycling on lead and lead-free (SnPb and SnAgCu) surface mount solder joints. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1815-1822 [Journal]
  11. Kendall D. Hester, Matthew P. Koehler, Hanna Kanciak-Chwialkowski, Brian H. Jones
    An assessment of the value of added screening of electronic components for commercial aerospace applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1823-1828 [Journal]
  12. Dominique Wojciechowski, Moses Chan, Fabrizio Martone
    Lead-free plastic area array BGAs and polymer stud grid arraysTM package reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1829-1839 [Journal]
  13. X. Tang, X. Baie, J. P. Colinge, P. Loumaye, C. Renaux, V. Bayot
    Influence of device geometry on SOI single-hole transistor characteristics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1841-1846 [Journal]
  14. Deborah M. Mechtel, Harry K. Charles Jr., Arthur S. Francomacaro
    The development of poled polyimide dielectric layers for simultaneous testing and light guiding applications in MCM-Ds. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1847-1855 [Journal]
  15. Mahamane Kader, Michel Lenczner, Zeljko Mrcarica
    Distributed control based on distributed electronic circuits: application to vibration control. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1857-1866 [Journal]
  16. Y. C. Chan, P. L. Tu, K. C. Hung
    Study of the self-alignment of no-flow underfill for micro-BGA assembly. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1867-1875 [Journal]
  17. Piotr Bratek, Andrzej Kos
    A method of thermal testing of microsystems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1877-1887 [Journal]
  18. Bing-Yue Tsui, Tsung-Ju Yang, Tzu-Kun Ku
    Impact of interface nature on deep sub-micron Al-plug resistance. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1889-1896 [Journal]
  19. Kun-Wei Lin, Kuo-Hui Yu, Wen-Lung Chang, Chih-Kai Wang, Wen-Huei Chiou, Wen-Chau Liu
    On the InGaP/InxGa1-xAs pseudomorphic high electron-mobility transistors for high-temperature operations. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1897-1902 [Journal]
  20. Lingfeng Mao, Yao Yang, Jian-Lin Wei, Heqiu Zhang, Mingzhen Xu, Changhua Tan
    Effect of SiO2/Si interface roughness on gate current. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1903-1907 [Journal]
  21. Fuchen Mu, Mingzhen Xu, Changhua Tan, Xiaorong Duan
    A new lifetime prediction method for hot-carrier degradation in n-MOSFETs with ultrathin gate oxides under Vg=Vd. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1909-1913 [Journal]
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