Journals in DBLP
Elyse Rosenbaum , Jie Wu Trap generation and breakdown processes in very thin gate oxides. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:625-632 [Journal ] Petteri Palm , Jarmo Määttänen , Aulis Tuominen , Eero Ristolainen Reliability of 80 mum pitch flip chip attachment on flex. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:633-638 [Journal ] Shatil Haque , Guo-Quan Lu Effects of device passivation materials on solderable metallization of IGBTs. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:639-647 [Journal ] Everett E. King , Ronald C. Lacoe , Janet Wang-Ratkovic Influence of the lightly doped drain resistance on the worst-case hot-carrier stress condition for NMOS devices. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:649-660 [Journal ] Jaakko Lenkkeri , Tuomo Jaakola Rapid power cycling of flip-chip and CSP components on ceramic substrates. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:661-668 [Journal ] Andrzej Dziedzic , Leszek J. Golonka , Jaroslaw Kita , Heiko Thust , Karl-Heinz Drue , Reinhard Bauer , Lars Rebenklau , Klaus-Jürgen Wolter Electrical and stability properties and ultrasonic microscope characterisation of low temperature co-fired ceramics resistors. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:669-676 [Journal ] S. C. Hung , P. J. Zheng , S. H. Ho , S. C. Lee , H. N. Chen , J. D. Wu Board level reliability of PBGA using flex substrate. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:677-687 [Journal ] Yung-Huei Lee , Tom Linton , Ken Wu , Neal Mielke Effect of trench edge on pMOSFET reliability. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:689-696 [Journal ] Takayuki Yamada , Masaru Moriwaki , Yoshinao Harada , Shinji Fujii , Koji Eriguchi Effects of the sputtering deposition process of metal gate electrode on the gate dielectric characteristics. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:697-704 [Journal ] Greg Hotchkiss , Gonzalo Amador , Darvin Edwards , Paul Hundt , Les Stark , Roger Stierman , Gail Heinen Wafer level packaging of a tape flip-chip chip scale packages. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:705-713 [Journal ] Harry K. Charles Jr. Tradeoffs in multichip module yield and cost with known good die probability and repair. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:715-733 [Journal ] Frank Stepniak Conversion of the under bump metallurgy into intermetallics: the impact on flip chip reliability. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:735-744 [Journal ] Kin P. Cheung Impact of ESD protection device trigger transient on the reliability of ultra-thin gate oxide. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:745-749 [Journal ] Terence B. Hook , David Harmon , Chuan Lin Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:751-765 [Journal ] D. Manic , J. Petr , R. S. Popovic Die stress drift measurement in IC plastic packages using the piezo-Hall effect. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:767-771 [Journal ] O. Mrooz , A. Kovalski , J. Pogorzelska , O. Shpotyuk , M. Vakiv , Bohdan S. Butkiewicz , J. Maciak Thermoelectrical degradation processes in NTC thermistors for in-rush current protection of electronic circuits. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:5, pp:773-777 [Journal ]