Journals in DBLP

Microelectronics Reliability
2001, volume: 41, number: 3

1. Koen G. Verhaege
   Editorial. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:3, pp:333- [Journal]
   
2. S. Voldman, W. Anderson, R. Ashton, M. Chaine, C. Duvvury, T. Maloney, E. Worley
   A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:3, pp:335-348 [Journal]
   
3. Jeremy C. Smith
   An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOS/ESD events. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:3, pp:349-357 [Journal]
   
4. Timothy J. Maloney, Wilson Kan
   Stacked PMOS clamps for high voltage power supply protection. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:3, pp:359-366 [Journal]
   
5. Warren R. Anderson, William M. Gonzalez, Sheera S. Knecht, Wendy Fowler
   Reliability considerations for ESD protection under wire bonding pads. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:3, pp:367-373 [Journal]
   
6. K. Bock, Bart Keppens, V. De Heyn, Guido Groeseneken, L. Y. Ching, A. Naem
   Influence of gate length on ESD-performance for deep submicron CMOS technology. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:3, pp:375-383 [Journal]
   
7. Harald Gossner, T. Müller-Lynch, K. Esmark, M. Stecher
   Wide range control of the sustaining voltage of electrostatic discharge protection elements realized in a smart power technology. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:3, pp:385-393 [Journal]
   
8. Gianluca Boselli, Stan Meeuwsen, Ton J. Mouthaan, Fred G. Kuper
   Investigations on double-diffused MOS transistors under ESD zap conditions. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:3, pp:395-405 [Journal]
   
9. L. G. Henry, M. A. Kelly, T. Diep, J. Barth
   Issues concerning charged device model ESD verification modules - the need to move to alumina. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2001, v:41, n:3, pp:407-415 [Journal]
   
10. Ming-Dou Ker, Yu-Yu Sung
    Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:3, pp:417-429 [Journal]
    
11. P. Schauer, Josef Sikula, P. Moravec
    Transport and noise properties of CdTe(Cl) crystals. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:3, pp:431-436 [Journal]
    
12. R. Dreesen, K. Croes, J. Manca, Ward De Ceuninck, Luc De Schepper, A. Pergoot, Guido Groeseneken
    A new degradation model and lifetime extrapolation technique for lightly doped drain nMOSFETs under hot-carrier degradation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:3, pp:437-443 [Journal]
    
13. A. H. Fischer, A. Abel, M. Lepper, A. E. Zitzelsberger, A. von Glasow
    Modeling bimodal electromigration failure distributions. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:3, pp:445-453 [Journal]
    
14. Keizo Yamada, Toyokazu Nakamura, Tohru Tsujide
    An in-line process monitoring method using electron beam induced substrate current. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:3, pp:455-459 [Journal]
    
15. Thomas D. Moore, John L. Jarvis
    Improved reliability in small multichip ball grid arrays. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:3, pp:461-469 [Journal]
    
16. Christian Rembe, Harald Aschemann, Stefan aus der Wiesche, Eberhard P. Hofer, Hélèn Debéda, Jürgen Mohr, Ulrike Wallrabe
    Testing and improvement of micro-optical-switch dynamics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:3, pp:471-480 [Journal]