Journals in DBLP

Microelectronics Reliability
2002, volume: 42, number: 12

1. Anri Nakajima, Quazi D. M. Khosru, Takashi Yoshimoto, Shin Yokoyama
   Atomic-layer-deposited silicon-nitride/SiO₂ stack--a highly potential gate dielectrics for advanced CMOS technology. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:12, pp:1823-1835 [Journal]
   
2. Deok-Hoon Kim, Peter Elenius, Michael Johnson, Scott Barrett
   Solder joint reliability of a polymer reinforced wafer level package. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:12, pp:1837-1848 [Journal]
   
3. A. Zehe
   Prediction of electromigration-void formation in copper conductors based on the electron configuration of matrix and solute atoms. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:12, pp:1849-1855 [Journal]
   
4. K. Y. Lim, X. Zhou
   An analytical effective channel-length modulation model for velocity overshoot in submicron MOSFETs based on energy-balance formulation. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:12, pp:1857-1864 [Journal]
   
5. Boualem Djezzar
   On the correlation between radiation-induced oxide- and border-trap effects in the gate-oxide nMOSFET's. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:12, pp:1865-1874 [Journal]
   
6. Dimitrios N. Kouvatsos
   On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:12, pp:1875-1882 [Journal]
   
7. Xingsheng Liu, Shuangyan Xu, Guo-Quan Lu, David A. Dillard
   Effect of substrate flexibility on solder joint reliability. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:12, pp:1883-1891 [Journal]
   
8. De-Shin Liu, Chin-Yu Ni
   The optimization design of bump interconnections in flip chip packages from the electrical standpoint. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:12, pp:1893-1901 [Journal]
   
9. Chin-Yu Ni, De-Shin Liu, Ching-Yang Chen
   Procedure for design optimization of a T-cap flip chip package. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:12, pp:1903-1911 [Journal]
   
10. Erja Jokinen, Eero Ristolainen
    Anisotropic conductive film flip chip joining using thin chips. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1913-1920 [Journal]
    
11. Frank Stepniak
    Failure criteria of flip chip joints during accelerated testing. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1921-1930 [Journal]
    
12. Dongji Xie, Sammy Yi
    Reliability studies and design improvement of mirror image CSP assembly. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1931-1937 [Journal]
    
13. Silke Liebert
    Encapsulation of naked dies for bulk silicon etching with TMAH. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1939-1944 [Journal]
    
14. Y. W. Chiu, Y. C. Chan, S. M. Lui
    Study of short-circuiting between adjacent joints under electric field effects in fine pitch anisotropic conductive adhesive interconnects. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1945-1951 [Journal]
    
15. Sunit Rane, Vijaya Puri
    Thin film, thick film microstrip band pass filter: a comparison and effect of bulk overlay. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1953-1958 [Journal]
    
16. Predrag Osmokrovic, Boris Loncar, Srboljub Stankovic, Aleksandra Vasic
    Aging of the over-voltage protection elements caused by over-voltages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1959-1966 [Journal]
    
17. E. M. Baskin
    Analysis of burn-in time using the general law of reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1967-1974 [Journal]
    
18. P. C. Lin, W. L. Pearn
    Testing process capability for one-sided specification limit with application to the voltage level translator. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1975-1983 [Journal]
    
19. B. L. Yang, N. W. Cheung, S. Denholm, J. Shao, H. Wong, P. T. Lai, Y. C. Cheng
    Ultra-shallow n⁺p junction formed by PH₃ and AsH₃ plasma immersion ion implantation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1985-1989 [Journal]
    
20. Shoucai Yuan, Changchun Zhu
    An IGBT DC subcircuit model with non-destructive parameters extraction and comparison with measurements. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1991-1996 [Journal]
    
21. Zhigang Song, Jiyan Dai, Shailesh Redkar
    Open contact analysis of single bit failure in 0.18 mum technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:1997-2001 [Journal]
    
22. V. O. Balitska, B. Butkievich, O. I. Shpotyuk, M. M. Vakiv
    On the analytical description of ageing kinetics in ceramic manganite-based NTC thermistors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:2003-2007 [Journal]
    
23. M. L. Huang, K. S. Chen, Y. H. Hung
    Integrated process capability analysis with an application in backlight module. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:12, pp:2009-2014 [Journal]