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Microelectronics Reliability
2003, volume: 43, number: 9-11

  1. Nathalie Labat, André Touboul
    Editorial. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1351-1352 [Journal]
  2. James H. Stathis, Barry P. Linder, R. Rodríguez, Salvatore Lombardo
    Reliability of ultra-thin oxides in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1353-1360 [Journal]
  3. D. Dufourt, J. L. Pelloie
    SOI design challenges. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1361-1367 [Journal]
  4. Lawrence C. Wagner
    Trends in Failure Analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1369-1375 [Journal]
  5. A. Andreini, C. Neva, L. Renard, G. Sironi, F. Speroni, L. Sponton, F. Tampellini, R. Tiziani
    Pad Over Active (POA) solutions for three metal level BCD5 mixed power process - Design and validation of ESD protections. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1377-1382 [Journal]
  6. Th. Nirschl, M. Ostermayr, A. Olbrich, D. Vietzke, M. Omer, C. Linnenbank, U. Schaper, Y. Pottgiesser, J. Pottgiesser, M. Johansson
    MALTY--A memory test structure for analysis in the early phase of the technology development. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1383-1387 [Journal]
  7. G. Aichmayr
    Correlation of gate oxide reliability and product tests on leading edge DRAM technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1389-1393 [Journal]
  8. A. Aal
    A procedure for reliability control and optimization of mixed-signal smart power CMOS pocesses. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1395-1400 [Journal]
  9. P. Charpenel, F. Davenel, R. Digout, M. Giraudeau, M. Glade, J. P. Guerveno, N. Guillet, A. Lauriac, S. Male, D. Manteigas
    The right way to assess electronic system reliability: FIDES. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1401-1404 [Journal]
  10. Yong-Ha Song, S. G. Kim, S. B. Lee, K. J. Rhee, T. S. Kim
    A study of considering the reliability issues on ASIC/Memory integration by SIP (System-in-Package) technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1405-1410 [Journal]
  11. G. Cassanelli, Fausto Fantini, G. Serra, S. Sgatti
    Reliability in automotive electronics: a case study applied to diesel engine control. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1411-1416 [Journal]
  12. Gerald Lucovsky
    Electronic structure of transition metal/rare earth alternative high-K gate dielectrics: interfacial band alignments and intrinsic defects. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1417-1426 [Journal]
  13. Jong-Tae Park, Nag Jong Choi, Chong-Gun Yu, Seok Hee Jeon, Jean-Pierre Colinge
    Increased hot carrier effects in Gate-All-Around SOI nMOSFET's. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1427-1432 [Journal]
  14. M. Fadlallah, C. Petit, A. Meinertzhagen, G. Ghibaudo, M. Bidaud, O. Simonetti, F. Guyader
    Influence of nitradation in ultra-thin oxide on the gate current degradation of N and PMOS devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1433-1438 [Journal]
  15. R. Rodríguez, James H. Stathis, Barry P. Linder, R. V. Joshi, C. T. Chuang
    Influence and model of gate oxide breakdown on CMOS inverters. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1439-1444 [Journal]
  16. F. Lime, G. Ghibaudo, B. Guillaumot
    Charge trapping in SiO2/HfO2/TiN gate stack. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1445-1448 [Journal]
  17. Yuan Li, Klaas Jelle Veenstra, Jerôme Dubois, Lei Peters-Wu, Agnes van Zomeren, Fred G. Kuper
    Reservoir effect and maximum allowed VIA misalignment for AlCu interconnect with tungsten VIA plug. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1449-1454 [Journal]
  18. S. Djoric-Veljkovic, I. Manic, V. Davidovic, S. Golubovic, Ninoslav Stojadinovic
    Effects of burn-in stressing on post-irradiation annealing response of power VDMOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1455-1460 [Journal]
  19. Young Pil Kim, Uin Chung, Joo Tae Moon, Sang U. Kim
    Electrical analysis of DRAM cell transistors for the root-cause addressing of the tRDL time-delay failure. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1461-1464 [Journal]
  20. Werner Frammelsberger, Guenther Benstetter, Thomas Schweinboeck, Richard J. Stamp, Janice Kiely
    Characterization of thin and ultra-thin SiO2 films and SiO2/Si interfaces with combined conducting and topographic atomic force microscopy. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1465-1470 [Journal]
  21. K. L. Pey, C. H. Tung, M. K. Radhakrishnan, L. J. Tang, Y. Sun, X. D. Wang, W. H. Lin
    Correlation of failure mechanism of constant-current-stress and constant-voltage-stress breakdowns in ultrathin gate oxides of nMOSFETs by TEM. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1471-1476 [Journal]
  22. Se Re Na Yun, Won Sub Park, Byung Ha Lee, Jong-Tae Park
    Hot electron induced punchthrough voltage of p-channel SOI MOSFET's at room and elevated temperatures. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1477-1482 [Journal]
  23. S. Aresu, Ward De Ceuninck, G. Knuyt, J. Mertens, J. Manca, Luc De Schepper, Robin Degraeve, Ben Kaczer, Marc D'Olieslaeger, Jan D'Haen
    A new method for the analysis of high-resolution SILC data. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1483-1488 [Journal]
  24. D. Zander, F. Saigné, A. Meinertzhagen, C. Petit
    Contribution of oxide traps on defect creation and LVSILC conduction in ultra thin gate oxide devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1489-1493 [Journal]
  25. Andreas Gehring, F. Jiménez-Molinos, Hans Kosina, A. Palma, F. Gámiz, Siegfried Selberherr
    Modeling of retention time degradation due to inelastic trap-assisted tunneling in EEPROM devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1495-1500 [Journal]
  26. M. Porti, M. Nafría, X. Aymerich
    Oxide conductivity increase during the progressive-breakdown of SiO2 gate oxides observed with C-AFM. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1501-1505 [Journal]
  27. Joachim C. Reiner
    Pre-breakdown leakage current fluctuations of thin gate oxide. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1507-1512 [Journal]
  28. B. Mongellaz, F. Marc, Y. Danto
    Ageing simulation of MOSFET circuit using a VHDL-AMS behavioural modelling: an experimental case study. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1513-1518 [Journal]
  29. D. Faure, D. Bru, C. Ali, C. Giret, K. Christensen
    Gate oxide breakdown characterization on 0.13mum CMOS technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1519-1523 [Journal]
  30. Jan Ackaert, Klara Bessemans, Eddy De Backer
    Charging induced damage by photoconduction through thick inter metal dielectrics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1525-1529 [Journal]
  31. Hamid Toutah, Boubekeur Tala-Ighil, Jean-François Llibre, B. Boudart, Taieb Mohammed-Brahim, Olivier Bonnaud
    Degradation in polysilicon thin film transistors related to the quality of the polysilicon material. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1531-1535 [Journal]
  32. S. Trinh, Markus P. J. Mergens, Koen G. Verhaege, Christian C. Russ, John Armer, Phillip Jozwiak, Bart Keppens, Russ Mohn, G. Taylor, Frederic De Ranter
    Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width scaling. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1537-1543 [Journal]
  33. Masashi Hayashi, Shinji Nakano, Tetsuaki Wada
    Dependence of copper interconnect electromigration phenomenon on barrier metal materials. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1545-1550 [Journal]
  34. M. Zecri, P. Besse, P. Givelin, M. Nayrolles, M. Bafleur, N. Nolhier
    Determination of the ESD Failure Cause Through its Signature. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1551-1556 [Journal]
  35. V. Dubec, Scrgey Bychikhin, M. Blaho, Dionyz Pogany, E. Gornik, J. Willemen, N. Qu, Wolfgang Wilkening, L. Zullino, A. Andreini
    A dual-beam Michelson interferometer for investigation of trigger dynamics in ESD protection devices under very fast TLP stress. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1557-1561 [Journal]
  36. Abdellatif Firiti, D. Faujour, G. Haller, J. M. Moragues, V. Goubier, Philippe Perdu, Felix Beaudoin, D. Lewis
    Short defect characterization based on TCR parameter extraction. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1563-1568 [Journal]
  37. M. S. B. Sowariraj, Theo Smedes, Cora Salm, Ton J. Mouthaan, Fred G. Kuper
    Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels -An explanation and die protection strategy. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1569-1575 [Journal]
  38. T. Beauchêne, D. Trémouilles, D. Lewis, Philippe Perdu, P. Fouillat
    Characterization of ESD induced defects using Photovoltaic Laser Stimulation (PLS). [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1577-1582 [Journal]
  39. Wen-Yu Lo, Ming-Dou Ker
    Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1583-1588 [Journal]
  40. Gaudenzio Meneghesso, N. Novembre, Enrico Zanoni, L. Sponton, L. Cerati, G. Croce
    Optimization of ESD protection structures suitable for BCD6 smart power technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1589-1594 [Journal]
  41. J. C. H. Phang, D. S. H. Chan, V. K. S. Ong, S. Kolachina, J. M. Chin, M. Palaniappan, G. Gilfeather, Y. X. Seah
    Single contact beam induced current phenomenon for microelectronic failure analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1595-1602 [Journal]
  42. Franco Stellari, Peilin Song, Moyra K. McManus, Alan J. Weger, Robert Gauthier, Kiran V. Chatty, Mujahid Muhammad, Pia Sanda, Philip Wu, Steve Wilson
    Latchup Analysis Using Emission Microscopy. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1603-1608 [Journal]
  43. Stefan Dilhaire, M. Amine Salhi, Stéphane Grauby, Wilfrid Claeys
    Laser Seebeck Effect Imaging (SEI) and Peltier Effect Imaging (PEI): complementary investigation methods. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1609-1613 [Journal]
  44. F. Darracq, H. Lapuyade, N. Buard, P. Fouillat, R. Dufayel, T. Carriere
    Low-cost backside laser test method to pre-characterize the COTS IC's sensitivity to Single Event Effects. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1615-1619 [Journal]
  45. P. LeCoupanec, William K. Lo, Keneth R. Wilsher
    An ultra-low dark-count and jitter, superconducting, single-photon detector for emission timing analysis of integrated circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1621-1626 [Journal]
  46. Katsuyoshi Miura, Tomoyuki Kobatake, Koji Nakamae, Hiromu Fujioka
    A low energy FIB processing, repair, and test system. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1627-1631 [Journal]
  47. F. Seifert, R. Weber, W. Mertin, E. Kubalek
    A new technique for contactless current contrast imaging of high frequency signals. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1633-1638 [Journal]
  48. M. Remmach, Romain Desplats, Felix Beaudoin, E. Frances, Philippe Perdu, D. Lewis
    Time Resolved Photoemission (PICA) - From the Physics to Practical Considerations. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1639-1644 [Journal]
  49. Hervé Deslandes, T. R. Lundquist
    Limitations to photon-emission microscopy when applied to "hot" devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1645-1650 [Journal]
  50. Maria Stangoni, Mauro Ciappa, Wolfgang Fichtner
    A New Procedure to Define the Zero-Field Condition and to Delineate pn-Junctions in Silicon Devices by Scanning Capacitance Microscopy. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1651-1656 [Journal]
  51. L. A. Knauss, A. Orozco, S. I. Woods, A. B. Cawthorne
    Advances in scanning SQUID microscopy for die-level and package-level fault isolation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1657-1662 [Journal]
  52. Romain Desplats, A. Eral, Felix Beaudoin, Philippe Perdu, Alan J. Weger, Moyra K. McManus, Peilin Song, Franco Stellari
    Faster IC Analysis with PICA Spatial Temporal Photon Correlation and CAD Autochanneling. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1663-1668 [Journal]
  53. Alberto Tosi, Franco Stellari, F. Zappa, S. Cova
    Backside Flip-Chip testing by means of high-bandwidth luminescence detection. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1669-1674 [Journal]
  54. B. Simmnacher, R. Weiland, J. Höhne, F. v. Feilitzsch, C. Hollerith
    Semiconductor material analysis based on microcalorimeter EDS. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1675-1680 [Journal]
  55. Felix Beaudoin, Romain Desplats, Philippe Perdu, Abdellatif Firiti, G. Haller, V. Pouget, D. Lewis
    From Static Thermal and Photoelectric Laser Stimulation (TLS/PLS) to Dynamic Laser Testing. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1681-1686 [Journal]
  56. Jon C. Lee, J. H. Chuang
    A Novel Application of C-AFM: Deep Sub-micron Single Probing for IC Failure Analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1687-1692 [Journal]
  57. Paul-Henri Albarède, S. Lavagne, C. Grosjean
    Strain investigation around shallow trench isolations : a LACBED Study. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1693-1698 [Journal]
  58. N. Lucarelli, M. Cavone, M. Muschitiello, D. Centrone, F. Corsi
    Thermally Induced Voltage Alteration (TIVA) applied to ESD induced failures. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1699-1704 [Journal]
  59. S. L. Delage, C. Dua
    Wide band gap semiconductor reliability : Status and trends. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1705-1712 [Journal]
  60. A. Curutchet, N. Malbert, N. Labat, A. Touboul, C. Gaquière, A. Minko, M. Uren
    Low frequency drain noise comparison of AlGaN/GaN HEMT's grown on silicon, SiC and sapphire substrates. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1713-1718 [Journal]
  61. J. Kuchenbecker, M. Borgarino, M. Zeuner, U. König, R. Plana, Fausto Fantini
    High Electric Field Induced Degradation of the DC Characteristics in Si/SiGe HEMT's. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1719-1723 [Journal]
  62. J. C. Martin, C. Maneux, N. Labat, A. Touboul, M. Riet, S. Blayac, M. Kahn, J. Godin
    1/f noise analysis of InP/InGaAs DHBTs submitted to bias and thermal stresses. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1725-1730 [Journal]
  63. M. Belhaj, C. Maneux, N. Labat, A. Touboul, P. Bove
    High current effects in InP/GaAsSb/InP DHBT: Physical mechanisms and parasitic effects. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1731-1736 [Journal]
  64. Gaudenzio Meneghesso, S. Levada, Enrico Zanoni, G. Scamarcio, G. Mura, Simona Podda, Massimo Vanzi, S. Du, I. Eliashevich
    Reliability of visible GaN LEDs in plastic package. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1737-1742 [Journal]
  65. L. Mendizabal, J. L. Verneuil, L. Béchou, C. Aupetit-Berthelemot, Y. Deshayes, F. Verdier, J. M. Dumas, Y. Danto, D. Laffitte, J. L. Goudard
    Impact of 1.55 mum laser diode degradation laws on fibre optic system performances using a system simulator. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1743-1749 [Journal]
  66. J. Van de Casteele, D. Laffitte, G. Gelly, C. Starck, M. Bettiati
    High reliability level demonstrated on 980nm laser diode. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1751-1754 [Journal]
  67. Kevin Sanchez, Romain Desplats, G. Perez, V. Pichetto, Felix Beaudoin, Philippe Perdu
    Solar Cell Analysis with Light Emission and OBIC Techniques. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1755-1760 [Journal]
  68. C. Gautier, J. Périnet, E. Nissou, D. Laffitte
    New method of qualification applied to optical amplifier with electronics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1761-1766 [Journal]
  69. J. L. Goudard, X. Boddaert, J. Périnet, D. Laffitte
    Reliability of optoelectronics components: towards new qualification practices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1767-1769 [Journal]
  70. G. Mura, Massimo Vanzi, Maria Stangoni, Mauro Ciappa, Wolfgang Fichtner
    On the behaviour of the selective iodine-based gold etch for the failure analysis of aged optoelectronic devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1771-1776 [Journal]
  71. G. Q. Zhang
    The challenges of virtual prototyping and qualification for future microelectronics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1777-1783 [Journal]
  72. P. Soussan, G. Lekens, R. Dreesen, Ward De Ceuninck, E. Beyne
    Advantage of In-situ over Ex-situ techniques as reliability tool: Aging kinetics of Imec's MCM-D discrete passives devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1785-1790 [Journal]
  73. P. Tropea, A. Mellal, J. Botsis
    Deformation and damage of a solder-copper joint. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1791-1796 [Journal]
  74. A. B. Horsfall, J. M. M. dos Santos, S. M. Soare, N. G. Wright, A. G. O'Neill, S. J. Bull, A. J. Walton, A. M. Gundlach, J. T. M. Stevenson
    Direct measurement of residual stress in integrated circuit interconnect features. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1797-1801 [Journal]
  75. G. Andriamonje, V. Pouget, Y. Ousten, D. Lewis, Y. Danto, J. M. Rampnoux, Y. Ezzahri, Stefan Dilhaire, Stéphane Grauby, Wilfrid Claeys
    Application of Picosecond Ultrasonics to Non-Destructive Analysis in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1803-1807 [Journal]
  76. O. Crépel, Romain Desplats, Y. Bouttement, Philippe Perdu, C. Goupil, Ph. Descamps, Felix Beaudoin, L. Marina
    Magnetic emission mapping for passive integrated components characterisation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1809-1814 [Journal]
  77. P. Rajamand, R. Tilgner, R. Schmidt, J. Baumann, P. Klofac, M. Rothenfusser
    Investigation of delaminations during thermal stress: scanning acoustic microscopy covering low and high temperatures. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1815-1820 [Journal]
  78. David Dalleau, Kirsten Weide-Zaage, Yves Danto
    Simulation of time depending void formation in copper, aluminum and tungsten plugged via structures. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1821-1826 [Journal]
  79. M. Krüger, J. Krinke, K. Ritter, B. Zierle, M. Weber
    Laser-assisted decapsulation of plastic-encapsulated devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1827-1831 [Journal]
  80. G. Lefranc, B. Weiss, C. Klos, J. Dick, G. Khatibi, H. Berg
    Aluminum bond-wire properties after 1 billion mechanical cycles. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1833-1838 [Journal]
  81. W. Kanert, H. Dettmer, B. Plikat, N. Seliger
    Reliability aspects of semiconductor devices in high temperature applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1839-1846 [Journal]
  82. F. Velardi, F. Iannuzzo, G. Busatto, J. Wyss, A. Sanseverino, A. Candelori, G. Currò, A. Cascio, F. Frisina
    Reliability of Medium Blocking Voltage Power VDMOSFET in Radiation Environment. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1847-1851 [Journal]
  83. Alexandrine Guédon, Eric Woirgard, Christian Zardini, Guillaume Simon
    Methodology to evaluate the correspondence between real conditions and accelerated tests of a thyristor system used in a power plant. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1853-1858 [Journal]
  84. E. Hornung, U. Scheuermann
    Reliability of low current electrical spring contacts in power modules. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1859-1864 [Journal]
  85. Yannick Rey-Tauriac, O. de Sagazan, M. Taurin, Olivier Bonnaud
    Robustness improvement of VDMOS transistors in Bipolar/CMOS/DMOS technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1865-1869 [Journal]
  86. G. Coquery, G. Lefranc, T. Licht, R. Lallemand, N. Seliger, H. Berg
    High temperature reliability on automotive power modules verified by power cycling tests up to 150degreeC. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1871-1876 [Journal]
  87. Alessandro Castellazzi, V. Kartal, R. Kraus, N. Seliger, M. Honsberg-Riedl, Doris Schmitt-Landsiedel
    Hot-Spot Meaurements and Analysis of Electro-Thermal Effects in Low-Voltage Power-MOSFET's. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1877-1882 [Journal]
  88. J. Vobecký, P. Hazdra
    Advanced Local Lifetime Control for Higher Reliability of Power Devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1883-1888 [Journal]
  89. T. Ayalew, Andreas Gehring, J. M. Park, Tibor Grasser, Siegfried Selberherr
    Improving SiC lateral DMOSFET reliability under high field stress. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1889-1894 [Journal]
  90. A. Icaza Deckelmann, Gerhard K. M. Wachutka, F. Hirler, J. Krumrey, R. Henninger
    Avalanche breakdown capability of Power DMOS Transistors and the Wunsch-Bell relation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1895-1900 [Journal]
  91. S. Azzopardi, E. Woirgard, J.-M. Vinassa, O. Briat, C. Zardini
    IGBT Power modules thermal characterization : what is the optimum between a low current - high voltage or a high current - low voltage test condition for the same electrical power? [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1901-1906 [Journal]
  92. G. Busatto, F. Iannuzzo, F. Velardi, M. Valentino, G. P. Pepe
    Non-Destructive Detection of Current Distribution in Power Modules based on Pulsed Magnetic Measurement. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1907-1912 [Journal]
  93. K. I. Nuttall, O. Buiu, V. V. N. Obreja
    Surface leakage current related failure of power silicon devices operated at high junction temperature. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1913-1918 [Journal]
  94. L. Buchaillot
    Feedback of MEMS reliability study on the design stage: a step toward Reliability Aided Design (RAD). [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1919-1928 [Journal]
  95. Cezary Sydlo, K. Mutamba, L. Divac Krnic, Bastian Mottet, Hans L. Hartnagel
    Reliability studies on integrated GaAs power-sensor structures using pulsed electrical stress. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1929-1933 [Journal]
  96. I. Boyer Heard, R. Coquillé, D. Rivière, P.-Y. Klimonda
    Characterization and reliability of a switch matrix based on MOEMS technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1935-1937 [Journal]
  97. A. Tetelin, C. Pellet, J.-Y. Delétage, B. Carbonne, Y. Danto
    Moisture diffusion in BCB resins used for MEMS packaging. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1939-1944 [Journal]
  98. S. Muratet, J. Y. Fourniols, G. Soto-Romero, A. Endemaño, A. Marty, M. Desmulliez
    MEMS reliability modelling methodology: application to wobble micromotor failure analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1945-1949 [Journal]
  99. Guillaume Marinier, Stefan Dilhaire, Luis David Patiño Lopez, Mohamed Benzohra
    Determination of passive SiO2-Au microstructure resonant frequencies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1951-1955 [Journal]
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