Journals in DBLP
Mark Zwolinski , M. S. Gaur Integrating testability with design space exploration. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:685-693 [Journal ] Reza Ghaffarian Qualification approaches and thermal cycle test results for CSP/BGA/FCBGA. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:695-706 [Journal ] Ru Huang , Jinyan Wang , Jin He , Min Yu , Xing Zhang , Yangyuan Wang Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET's (n-DTMOSFET) measured by gated-diode configuration. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:707-711 [Journal ] Summer F. C. Tseng , Wei-Ting Kary Chien , Bing-Chu Cai Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:713-724 [Journal ] Xiaofang Gao , Juin J. Liou , Joe Bernier , Gregg Croft , Waisum Wong , Satya Vishwanathan Optimization of on-chip ESD protection structures for minimal parasitic capacitance. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:725-733 [Journal ] Chihoon Lee , Donggun Park , Hyeong Joon Kim , Wonshik Lee Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:735-739 [Journal ] Tong Yan Tee , Chek Lim Kho , Daniel Yap , Carol Toh , Xavier Baraton , Zhaowei Zhong Reliability assessment and hygroswelling modeling of FCBGA with no-flow underfill. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:741-749 [Journal ] Qian Wang , Naoe Hosoda , Toshihiro Itoh , Tadatomo Suga Reliability of Au bump-Cu direct interconnections fabricated by means of surface activated bonding method. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:751-756 [Journal ] K. S. Kim , C. H. Yu , N. H. Kim , N. K. Kim , H. J. Chang , E. G. Chang Isothermal aging characteristics of Sn-Pb micro solder bumps. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:757-763 [Journal ] W. D. van Driel , G. Q. Zhang , J. H. J. Janssen , L. J. Ernst , F. Su , Kerm Sin Chian , Sung Yi Prediction and verification of process induced warpage of electronic packages. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:765-774 [Journal ] Ping Zhao , Michael G. Pecht Field failure due to creep corrosion on components with palladium pre-plated leadframes. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:775-783 [Journal ] Z. Zhao Thermal design of a broadband communication system with detailed modeling of TBGA packages. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:785-793 [Journal ] Vencislav Valchev , Alex Van den Bossche Accurate natural convection modelling for magnetic components. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:795-802 [Journal ] T. Y. Lin , K. L. Davison , W. S. Leong , Simon Chua , Y. F. Yao , J. S. Pan , J. W. Chai , K. C. Toh , W. C. Tjiu Surface topographical characterization of silver-plated film on the wedge bondability of leaded IC packages. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:803-809 [Journal ] T. Y. Lin , C. M. Fang , Y. F. Yao , K. H. Chua Development of the green plastic encapsulation for high density wirebonded leaded packages. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:811-817 [Journal ] Mile K. Stojcev High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test; R. Dean Adams, Kluwer Academic Publishers, Boston, 2003, Hardcover, pp 247, plus XIII, ISBN 1-4020-7255-4. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:5, pp:819- [Journal ]