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Journals in DBLP

Microelectronics Reliability
2004, volume: 44, number: 3

  1. Baozhen Li, Timothy D. Sullivan, Tom C. Lee, Dinesh Badami
    Reliability challenges for copper interconnects. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:365-380 [Journal]
  2. Ming-C. Cheng, Feixia Yu, Lin Jun, Min Shen, Goodarz Ahmadi
    Steady-state and dynamic thermal models for heat flow analysis of silicon-on-insulator MOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:381-396 [Journal]
  3. Gregory Freeman, Jae-Sung Rieh, Zhijian Yang, Fernando J. Guarín
    Reliability and performance scaling of very high speed SiGe HBTs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:397-410 [Journal]
  4. K.-H. Allers
    Prediction of dielectric reliability from I-V characteristics: Poole-Frenkel conduction mechanism leading to sqrt(E) model for silicon nitride MIM capacitor. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:411-423 [Journal]
  5. Kyungmee O. Kim, Way Kuo, Wen Luo
    A relation model of gate oxide yield and reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:425-434 [Journal]
  6. Xiangbin Zeng, X. W. Sun, Junfeng Li, Johnny K. O. Sin
    Improving reliability of poly-Si TFTs with channel layer and gate oxide passivated by NH3/N2O plasma. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:435-442 [Journal]
  7. Pierre Temple-Boyer, J. Launay, I. Humenyuk, T. Do Conto, A. Martinez, C. Bériet, A. Grisel
    Study of front-side connected chemical field effect transistor for water analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:443-447 [Journal]
  8. S. Nakajima, S. Nakamura, T. Ueki, T. Sakai
    Sample preparation techniques for physical analysis of VLSIs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:449-458 [Journal]
  9. Jie-Hua Zhao
    A three-parameter Weibull-like fitting function for flip-chip die strength data. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:459-470 [Journal]
  10. Yu Gu, Toshio Nakamura
    Interfacial delamination and fatigue life estimation of 3D solder bumps in flip-chip packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:471-483 [Journal]
  11. S. Nurmi, J. Sundelin, Eero Ristolainen, T. Lepistö
    The effect of solder paste composition on the reliability of SnAgCu joints. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:485-494 [Journal]
  12. S. C. Tan, Y. C. Chan, Y. W. Chiu, C. W. Tan
    Thermal stability performance of anisotropic conductive film at different bonding temperatures. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:495-503 [Journal]
  13. M. A. Uddin, M. O. Alam, Y. C. Chan, H. P. Chan
    Adhesion strength and contact resistance of flip chip on flex packages--effect of curing degree of anisotropic conductive film. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:505-514 [Journal]
  14. Tadanori Shimoto, Katsumi Kikuchi, Kazuhiro Baba, Koji Matsui, Hirokazu Honda, Keiichiro Kata
    High-performance FCBGA based on multi-layer thin-substrate packaging technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:515-520 [Journal]
  15. Beth Keser, Li Wetz, Jerry White
    WL-CSP reliability with various solder alloys and die thicknesses. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:521-531 [Journal]
  16. Li Zhang, Vivek Arora, Luu Nguyen, Nikhil Kelkar
    Numerical and experimental analysis of large passivation opening for solder joint reliability improvement of micro SMD packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:533-541 [Journal]
  17. R. Khlil, A. El Hdiy, A. F. Shulekin, S. E. Tyaginov, M. I. Vexler
    Soft breakdown of MOS tunnel diodes with a spatially non-uniform oxide thickness. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:543-546 [Journal]
  18. Mile K. Stojcev
    Power-Constrained Testing of VLSI Circuits. Nikola Nikolici, Bashir M. Al-Hashimi. Kluwer Academic Publishers, Boston, 2003. Hardcover, pp 178, plus XI, ISBN 1-4020-7235-X. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:3, pp:547-548 [Journal]
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