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Journals in DBLP

Microelectronics Reliability
2005, volume: 45, number: 3-4

  1. Joachim N. Burghartz
    Review of add-on process modules for high-frequency silicon technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:409-418 [Journal]
  2. John S. Suehle, B. Zhu, Y. Chen, Joseph B. Bernstein
    Detailed study and projection of hard breakdown evolution in ultra-thin gate oxides. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:419-426 [Journal]
  3. Bonnie E. Weir, Che-Choi Leung, Paul J. Silverman, Muhammad A. Alam
    Gate dielectric breakdown in the time-scale of ESD events. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:427-436 [Journal]
  4. Steven H. Voldman
    A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II - Latchup. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:437-455 [Journal]
  5. V. A. Vashchenko, P. Hopper
    Bipolar SCR ESD devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:457-471 [Journal]
  6. Ji-hyuk Lim, Keon Kuk, Seung-joo Shin, Seog-soon Baek, Young-Jae Kim, Jong-woo Shin, Yong-soo Oh
    Failure mechanisms in thermal inkjet printhead analyzed by experiments and numerical simulation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:473-478 [Journal]
  7. C. Petit, A. Meinertzhagen, D. Zander, O. Simonetti, M. Fadlallah, T. Maurel
    Low voltage SILC and P- and N-MOSFET gate oxide reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:479-485 [Journal]
  8. D. Goguenheim, A. Bravaix, S. Gomri, J. M. Moragues, C. Monserie, N. Legrand, P. Boivin
    Impact of wafer charging on hot carrier reliability and optimization of latent damage detection methodology in advanced CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:487-492 [Journal]
  9. I. Cortés, J. Roig, D. Flores, J. Urresti, S. Hidalgo, J. Rebollo
    Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:493-498 [Journal]
  10. Alessandro Marras, Ilaria De Munari, Davide Vescovi, Paolo Ciampolini
    Impact of gate-leakage currents on CMOS circuit performance. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:499-506 [Journal]
  11. Ramana Murthy, Y. W. Chen, A. Krishnamoorthy, X. T. Chen
    SiLKTM etch optimization and electrical characterization for 0.13 mum interconnects. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:507-516 [Journal]
  12. C. F. Tsang, C. K. Chang, A. Krishnamoorthy, K. Y. Ee, Y. J. Su, H. Y. Li, W. H. Li, L. Y. Wong
    A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:517-525 [Journal]
  13. J. de Vries, J. van Delft, C. Slob
    100 mum Pitch flip chip on foil assemblies with adhesive interconnections. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:527-534 [Journal]
  14. Ying Wang, Changchun Zhu, Chunyu Wu, Junhua Liu
    Improving reliability of beveled power semiconductor devices passivated by SIPOS. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:535-539 [Journal]
  15. N. Nenadovic, V. Cuoco, S. J. C. H. Theeuwen, L. K. Nanver, H. Schellevis, G. Spierings, H. F. F. Jos, J. W. Slotboom
    Electrothermal characterization of silicon-on-glass VDMOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:541-550 [Journal]
  16. Ivan N. Ndip, Grit Sommer, Werner John, Herbert Reichl
    Characterization of bump arrays at RF/microwave frequencies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:551-558 [Journal]
  17. Yi Tao, Ajay P. Malshe
    Theoretical investigation on hermeticity testing of MEMS packages based on MIL-STD-883E. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:559-566 [Journal]
  18. Tadanori Shimoto, Kazuhiro Baba, Koji Matsui, Jun Tsukano, Takehiko Maeda, Kenji Oyachi
    Ultra-thin high-density LSI packaging substrate for advanced CSPs and SiPs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:567-574 [Journal]
  19. Yi-Shao Lai, Tong Hong Wang
    Verification of submodeling technique in thermomechanical reliability assessment of flip-chip package assembly. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:575-582 [Journal]
  20. L. Frisk, Eero Ristolainen
    Flip chip attachment on flexible LCP substrate using an ACF. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:583-588 [Journal]
  21. M. J. Rizvi, Y. C. Chan, C. Bailey, H. Lu
    Study of anisotropic conductive adhesive joint behavior under 3-point bending. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:589-596 [Journal]
  22. Hua Lu, Jesse Zhou, Rich Golek, Ming Zhou
    Hybrid reliability assessment for packaging prototyping. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:597-609 [Journal]
  23. Dongsu Ryu, Seogweon Chang
    Novel concepts for reliability technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:611-622 [Journal]
  24. L. Zhang, G. Subbarayan, B. C. Hunter, D. Rose
    Response surface models for efficient, modular estimation of solder joint reliability in area array packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:623-635 [Journal]
  25. Jinwon Joo, Seungmin Cho, Bongtae Han
    Characterization of flexural and thermo-mechanical behavior of plastic ball grid package assembly using moiré interferometry. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:637-646 [Journal]
  26. K. S. Kim, K. W. Ryu, C. H. Yu, J. M. Kim
    The formation and growth of intermetallic compounds and shear strength at Sn-Zn solder/Au-Ni-Cu interfaces. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:647-655 [Journal]
  27. C. T. Pan, P. J. Cheng, M. F. Chen, C. K. Yen
    Intermediate wafer level bonding and interface behavior. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:657-663 [Journal]
  28. Tuomas F. Waris, Markus P. K. Turunen, Tomi Laurila, Jorma K. Kivilahti
    Evaluation of electrolessly deposited NiP integral resistors on flexible polyimide substrate. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:665-673 [Journal]
  29. Sam Siau, Johan De Baets, André Van Calster, Leon Heremans, Sammy Tanghe
    Processing quality results for electroless/electroplating of high-aspect ratio plated through holes in industrially produced printed circuit boards. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:675-687 [Journal]
  30. Yi He
    Chemical and diffusion-controlled curing kinetics of an underfill material. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:689-695 [Journal]
  31. T. Islam, C. Pramanik, H. Saha
    Modeling, simulation and temperature compensation of porous polysilicon capacitive humidity sensor using ANN technique. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:697-703 [Journal]
  32. Sasa Radovanovic, Anne-Johan Annema, Bram Nauta
    Bandwidth of integrated photodiodes in standard CMOS for CD/DVD applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:705-710 [Journal]
  33. Luke Maguire, Masud Behnia, Graham Morrison
    Systematic evaluation of thermal interface materials - a case study in high power amplifier design. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:711-725 [Journal]
  34. Maria Teresa Sanz, Santiago Celma, Belén Calvo, Juan P. Alegre
    MOS current divider based PGA. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:3-4, pp:727-732 [Journal]
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