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Journals in DBLP

Microelectronics Reliability
2005, volume: 45, number: 2

  1. Wolfgang Stadler
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:199-200 [Journal]
  2. Jeremy C. Smith, Gianluca Boselli
    A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:201-210 [Journal]
  3. Michael Stockinger, James W. Miller, Michael G. Khazhinsky, Cynthia A. Torres, James C. Weldon, Bryan D. Preble, Martin J. Bayer, Matthew D. Akers, Vishnu G. Kamat
    Advanced rail clamp networks for ESD protection. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:211-222 [Journal]
  4. Michael Chaine, James Davis, Al Kearney
    TLP analysis of 0.125 mum CMOS ESD input protection circuit. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:223-231 [Journal]
  5. Florence Azaïs, B. Caillard, S. Dournelle, P. Salomé, Pascal Nouet
    A new multi-finger SCR-based structure for efficient on-chip ESD protection. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:233-243 [Journal]
  6. Sami Hyvonen, Sopan Joshi, Elyse Rosenbaum
    Comprehensive ESD protection for RF inputs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:245-254 [Journal]
  7. Vesselin K. Vassilev, S. Thijs, P. L. Segura, P. Wambacq, Paul Leroux, Guido Groeseneken, M. I. Natarajan, H. E. Maes, Michiel Steyaert
    ESD-RF co-design methodology for the state of the art RF-CMOS blocks. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:255-268 [Journal]
  8. Wolfgang Stadler, K. Esmark, K. Reynders, M. Zubeidat, M. Graf, Wolfgang Wilkening, J. Willemen, N. Qu, S. Mettler, M. Etherton
    Test circuits for fast and reliable assessment of CDM robustness of I/O stages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:269-277 [Journal]
  9. Heinrich Wolf, Horst A. Gieser, Wolfgang Stadler, Wolfgang Wilkening
    Capacitively coupled transmission line pulsing cc-TLP--a traceable and reproducible stress method in the CDM-domain. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:279-285 [Journal]
  10. Andrew Olney, Brad Gifford, John Guravage, Alan Righter
    Real-world printed circuit board ESD failures. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:287-295 [Journal]
  11. S. Bargstädt-Franke, Wolfgang Stadler, K. Esmark, M. Streibl, K. Domanski, Horst A. Gieser, Heinrich Wolf, W. Bala
    Transient latch-up: experimental analysis and device simulation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:297-304 [Journal]
  12. Al Wallash
    ESD SPICE model and measurements for a hard disk drive. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:305-311 [Journal]
  13. M. Streibl, F. Zängl, K. Esmark, R. Schwencker, Wolfgang Stadler, Harald Gossner, S. Drüen, D. Schmitt-Landsiedel
    High abstraction level permutational ESD concept analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:313-321 [Journal]
  14. Steven H. Voldman
    A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:323-340 [Journal]
  15. N. A. Hastas, N. Archontas, C. A. Dimitriadis, G. Kamarinos, T. Nikolaidis, N. Georgoulas, A. Thanailakis
    Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:341-348 [Journal]
  16. Tsz Yin Man, Mansun Chan
    A 2-bit highly scalable nonvolatile memory cell with two electrically isolated charge trapping sites. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:349-354 [Journal]
  17. P. C. Adell, R. D. Schrimpf, C. R. Cirba, W. T. Holman, X. Zhu, H. J. Barnaby, O. Mion
    Single event transient effects in a voltage reference. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:355-359 [Journal]
  18. S. H. Choa
    Reliability of vacuum packaged MEMS gyroscopes. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:361-369 [Journal]
  19. Chang-Lin Yeh, Yi-Shao Lai
    Transient analysis of the impact stage of wirebonding on Cu/low-K wafers. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:371-378 [Journal]
  20. Daniel T. Rooney, DeePak Nager, David Geiger, Dongkai Shanguan
    Evaluation of wire bonding performance, process conditions, and metallurgical integrity of chip on board wire bonds. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:379-390 [Journal]
  21. E. Misra, Md M. Islam, Mahbub Hasan, H. C. Kim, T. L. Alford
    Percolative approach for failure time prediction of thin film interconnects under high current stress. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:391-395 [Journal]
  22. Vitezslav Benda
    A note on trap recombination in high voltage device structures. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:397-401 [Journal]
  23. Mile K. Stojcev
    Data communication. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:403-404 [Journal]
  24. Mile K. Stojcev
    Yale N. Patt and Sanjay J. Patel, Introduction to Computing Systems: From Bits and Gates to C and Beyond Second edition, McGraw-Hill Higher Education, Boston (2004) ISBN 0-07-121503-4 Softcover, pp 632, plus XXIV. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:405-406 [Journal]
  25. Mile K. Stojcev
    Vadim Ivanov, Igor Filanovsky, Operational Amplifier Speed and Accuracy Improvement: Analog Circuit Design with Structural Methodology, Kluwer Academic Publishers, Boston, 2004, Hardcover, pp 194, plus XIV, ISBN 1-4020-7772-6. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:407-408 [Journal]
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