Journals in DBLP

Microelectronics Reliability
2006, volume: 46, number: 7

1. V. Filip, Hei Wong, D. Nicolaescu
   Definition of curve fitting parameter to study tunneling and trapping of electrons in Si/ultra-thin SiO₂/metal structures. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:7, pp:1027-1034 [Journal]
   
2. S. E. Tyaginov, M. I. Vexler, A. F. Shulekin, I. V. Grekhov
   The post-damage behavior of a MOS tunnel emitter transistor. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:7, pp:1035-1041 [Journal]
   
3. Shih-Hung Chen, Ming-Dou Ker
   Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:7, pp:1042-1049 [Journal]
   
4. A. Emre Yarimbiyik, Harry A. Schafft, Richard A. Allen, Mona E. Zaghloul, David L. Blackburn
   Modeling and simulation of resistivity of nanometer scale copper. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:7, pp:1050-1057 [Journal]
   
5. Henry Y. Lu, Haluk Balkan, K. Y. Simon Ng
   Microstructure evolution of the Sn-Ag-y%Cu interconnect. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:7, pp:1058-1070 [Journal]
   
6. Päivi H. Karjalainen, Eero Ristolainen
   Balancing temperature dependence of on-wafer SOS inductors. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:7, pp:1071-1079 [Journal]
   
7. K. S. Kim, C. H. Yu, J. M. Yang
   Tin whisker formation of lead-free plated leadframes. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:7, pp:1080-1086 [Journal]
   
8. Dae Whan Kim, Byung-Seon Kong
   The effect of hygro-mechanical and thermo-mechanical stress on delamination of gold bump. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:7, pp:1087-1094 [Journal]
   
9. M. Ullán, M. Lozano, M. Chmeissani, G. Blanchot, Enric Cabruja, J. García, M. Maiorino, R. Martínez, G. Pellegrini, C. Puigdengoles
   Test structure assembly for bump bond yield measurement on high density flip chip technologies. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:7, pp:1095-1100 [Journal]
   
10. Yong Ding, Jang-Kyo Kim, Pin Tong
    Effects of bonding force on contact pressure and frictional energy in wire bonding. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1101-1112 [Journal]
    
11. M. Yamashita, K. Suganuma
    Degradation by Sn diffusion applied to surface mounting with Ag-epoxy conductive adhesive with joining pressure. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1113-1118 [Journal]
    
12. Dong-Jun Lee, Hyo S. Lee
    Major factors to the solder joint strength of ENIG layer in FC BGA package. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1119-1127 [Journal]
    
13. Xia Liu, Valmiki K. Sooklal, Melody A. Verges, Michael C. Larson
    Experimental study and life prediction on high cycle vibration fatigue in BGA packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1128-1138 [Journal]
    
14. Chi-Hui Chien, Thaiping Chen, Yung-Chang Chen, Yii-Tay Chiou, Chi-Chang Hsieh, Yii-Der Wu
    Stability of the warpage in a PBGA package subjected to hygro-thermal loading. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1139-1147 [Journal]
    
15. Hua Lu, Helen Shi, Ming Zhou
    Thermally induced deformation of solder joints in real packages: Measurement and analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1148-1159 [Journal]
    
16. Desmond Y. R. Chong, F. X. Che, John H. L. Pang, Kellin Ng, Jane Y. N. Tan, Patrick T. H. Low
    Drop impact reliability testing for lead-free and lead-based soldered IC packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1160-1171 [Journal]
    
17. Chang-Lin Yeh, Yi-Shao Lai, Chin-Li Kao
    Evaluation of board-level reliability of electronic packages under consecutive drops. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1172-1182 [Journal]
    
18. Y. H. Hung, M. L. Huang, C. H. Chang
    Optimizing the controller IC for micro HDD process based on Taguchi methods. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1183-1188 [Journal]
    
19. K. S. Chen, C. H. Wang, H. T. Chen
    A MAIC approach to TFT-LCD panel quality improvement. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1189-1198 [Journal]
    
20. Jianhui Xing, Hong Wang, Shiyuan Yang
    Constructing IP cores' transparency paths for SoC test access using greedy search. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1199-1208 [Journal]
    
21. L. Chen, M. M. El-Gomati
    Stabilized emission from micro-field emitter for electron microscopy. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1209-1213 [Journal]
    
22. Mile K. Stojcev
    R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation (second ed.), Wiley Interscience & IEEE Press (2005) ISBN 0-471-70055-X Hardcover, pp 1039, plus XXXIII. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1214-1215 [Journal]