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Journals in DBLP

Microelectronics Reliability
2007, volume: 47, number: 1

  1. Hei Wong, V. Filip, C. K. Wong, P. S. Chung
    Silicon integrated photonics begins to revolutionize. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:1-10 [Journal]
  2. Viktor Sverdlov, Hans Kosina, Siegfried Selberherr
    Modeling current transport in ultra-scaled field-effect transistors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:11-19 [Journal]
  3. T. Hattori, H. Nohira, S. Shinagawa, M. Hori, M. Kase, T. Maruizumi
    Angle-resolved photoelectron spectroscopy on gate insulators. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:20-26 [Journal]
  4. Ming-Dou Ker, Wei-Jen Chang
    Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:27-35 [Journal]
  5. Sergey Shaimeev, Vladimir Gritsenko, Kaupo Kukli, Hei Wong, Eun-Hong Lee, Chungwoo Kim
    Single band electronic conduction in hafnium oxide prepared by atomic layer deposition. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:36-40 [Journal]
  6. C. Leyris, F. Martinez, A. Hoffmann, M. Valenza, J. C. Vildeuil
    N-MOSFET oxide trap characterization induced by nitridation process using RTS noise analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:41-45 [Journal]
  7. Y. Fu, H. Wong, J. J. Liou
    Characterization and modeling of flicker noise in junction field-effect transistor with source and drain trench isolation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:46-50 [Journal]
  8. Milan Jevtic, Jovan M. Hadzi-Vukovic
    Study of the electrical cycling stressed large area Schottky diodes using I-V and noise measurements. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:51-58 [Journal]
  9. M. A. Belaïd, K. Ketata, M. Gares, K. Mourgues, M. Masmoudi, J. Marcon
    Comparative analysis of RF LDMOS capacitance reliability under accelerated ageing tests. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:59-64 [Journal]
  10. Giovanna Sozzi, Roberto Menozzi
    A review of the use of electro-thermal simulations for the analysis of heterostructure FETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:65-73 [Journal]
  11. Hirotaka Komoda, Chie Moritani, Kazutaka Takahashi, Heiji Watanabe, Kiyoshi Yasutake
    Sample tilting technique for preventing electrostatic discharge during high-current FIB gas-assisted etching with XeF2. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:74-81 [Journal]
  12. Hongfei Liu, Alin Hou, Hongbo Zhang, Daming Zhang, Maobin Yi
    A voltage calibration technique of electro-optic probing for characterization internal to IC's chip. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:82-87 [Journal]
  13. Yuki Fukuda, Michael D. Osterman, Michael G. Pecht
    The impact of electrical current, mechanical bending, and thermal annealing on tin whisker growth. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:88-92 [Journal]
  14. J. Varghese, A. Dasgupta
    Test methodology for durability estimation of surface mount interconnects under drop testing conditions. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:93-103 [Journal]
  15. Yi-Shao Lai, Tong Hong Wang
    Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:104-110 [Journal]
  16. Yi-Shao Lai, Tong Hong Wang, Han-Hui Tsai, Ming-Hwa R. Jen
    Cyclic bending reliability of wafer-level chip-scale packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:111-117 [Journal]
  17. J. G. Lee, K. N. Subramanian
    Effects of TMF heating rates on damage accumulation and resultant mechanical behavior of Sn-Ag based solder joints. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:118-131 [Journal]
  18. S. Stoyanov, R. Kay, C. Bailey, M. Desmulliez
    Computational modelling for reliable flip-chip packaging at sub-100mum pitch using isotropic conductive adhesives. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:132-141 [Journal]
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