Journals in DBLP
Daniela De Venuto , Tom Chen International Symposium on Quality Electronic Design. [Citation Graph (0, 0)][DBLP ] Journal ] Huifang Qin , Yu Cao , Dejan Markovic , Andrei Vladimirescu , Jan M. Rabaey Standby supply voltage minimization for deep sub-micron SRAM. [Citation Graph (0, 0)][DBLP ] Journal ] Bhaskar Chatterjee , Manoj Sachdev , Ram Krishnamurthy Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. [Citation Graph (0, 0)][DBLP ] Journal ] Daniela De Venuto Testing high resolution SigmaDelta ADC's by using the quantizer input as test access. [Citation Graph (0, 0)][DBLP ] Journal ] Achintya Halder , Abhijit Chatterjee Test generation for specification test of analog circuits using efficient test response observation methods. [Citation Graph (0, 0)][DBLP ] Journal ] Cristian Grecu , Partha Pratim Pande , André Ivanov , Res Saleh Timing analysis of network on chip architectures for MP-SoC platforms. [Citation Graph (0, 0)][DBLP ] Journal ] Meigen Shen , Jian Liu , Li-Rong Zheng , Esa Tjukanoff , Hannu Tenhunen Robustness enhancement through chip-package co-design for high-speed electronics. [Citation Graph (0, 0)][DBLP ] Journal ] Sobeeh Almukhaizim , Petros Drineas , Yiorgos Makris Compaction-based concurrent error detection for digital circuits. [Citation Graph (0, 0)][DBLP ] Journal ] Volkan Kursun , Vivek De , Eby G. Friedman , Siva G. Narendra Monolithic voltage conversion in low-voltage CMOS technologies. [Citation Graph (0, 0)][DBLP ] Journal ] 