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Journals in DBLP

Computers and Artificial Intelligence
2004, volume: 23, number: 5

  1. A. Parreira, João Paulo Teixeira, Marcelino B. Santos
    Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In FPGAs. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  2. Abhijit Ray, Wu Jigang, Thambipillai Srikanthan
    Knapsack Model and Algorithm for Hardware/Software Partitioning Problem. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  3. Heikki Kariniemi, Jari Nurmi
    Performance Evaluation and Implementation of Two Adaptive Routing Algorithms for XGFT Networks. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  4. Nele Mentens, Siddika Berna Örs, Bart Preneel, Joos Vandewalle
    An FPGA Implementation of a Montgomery Multiplier Over GF(2^m). [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  5. Solaiman Rahim, Bruno Rouzeyre, Lionel Torres
    A Flip-Flop Matching Engine to Verify Sequential Optimizations. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  6. Thomas Kottke, Andreas Steininger
    A Generic Dual Core Architecture with Error Containment. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  7. Lukás Sekanina, Stepan Friedl
    An Evolvable Combinational Unit for FPGAs. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  8. Milos Drutarovský, Martin Simka, Viktor Fischer, Frederic Celle
    A Simple PLL-Based True Random Number Generator for Embedded Digital Systems. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
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