
Journals in DBLP
Integration 2007, volume: 40, number: 4
 Igor L. Markov, Louis Scheffer, Dirk Stroobandt
Special issue on SystemLevel Interconnect Prediction. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:381 [Journal]
 Wim Heirman, Joni Dambre, I. Artundo, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan M. Van Campenhout
Predicting reconfigurable interconnect performance in distributed sharedmemory systems. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:382393 [Journal]
 Brajesh Kumar Kaushik, Sankar Sarkar, R. P. Agarwal
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:394405 [Journal]
 Yaoguang Wei, Sheqin Dong, Xianlong Hong
APWLY: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:406419 [Journal]
 Tao Wan, Malgorzata ChrzanowskaJeske
A novel netdegree distribution model and its application to floorplanning benchmark generation. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:420433 [Journal]
 Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman
Predictions of CMOS compatible onchip optical interconnect. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:434446 [Journal]
 João M. S. Silva, L. Miguel Silveira
Substrate model extraction using finite differences and parallel multigrid. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:447460 [Journal]
 Magdy A. ElMoursy, Eby G. Friedman
Wire shaping of RLC interconnects. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:461472 [Journal]
 HyunSung Kim, SungWoon Lee
LFSR multipliers over GF(2^{m}) defined by allone polynomial. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:473478 [Journal]
 Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet
A fast pipelined multimode DES architecture operating in IP representation. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:479489 [Journal]
 Ming Z. Zhang, Vijayan K. Asari
An efficient multiplierless architecture for 2D convolution with quadrant symmetric kernels. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:490502 [Journal]
 Jing Huang, Mariam Momenzadeh, Fabrizio Lombardi
Analysis of missing and additional cell defects in sequential quantumdot cellular automata. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:503515 [Journal]
 Jeffrey Fan, Sheldon X.D. Tan, Yici Cai, Xianlong Hong
Partitioningbased decoupling capacitor budgeting via sequence of linear programming. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:516524 [Journal]
 Soumen Maity, Amiya Nayak, S. Ramsundar
Characterization, testing and reconfiguration of faults in mesh networks. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:525535 [Journal]
 Omar S. Elkeelany, Ghulam Chaudhry
Integrating firewire peripheral interface with an ethernet custom network processor. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:536548 [Journal]
 Mustafa Gök
A novel IEEE rounding algorithm for highspeed floatingpoint multipliers. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:549560 [Journal]
 Vishal Khandelwal, Ankur Srivastava
Active mode leakage reduction using finegrained forward body biasing strategy. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:561570 [Journal]
