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Journals in DBLP

Integration
2007, volume: 40, number: 4

  1. Igor L. Markov, Louis Scheffer, Dirk Stroobandt
    Special issue on System-Level Interconnect Prediction. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:381- [Journal]
  2. Wim Heirman, Joni Dambre, I. Artundo, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan M. Van Campenhout
    Predicting reconfigurable interconnect performance in distributed shared-memory systems. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:382-393 [Journal]
  3. Brajesh Kumar Kaushik, Sankar Sarkar, R. P. Agarwal
    Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:394-405 [Journal]
  4. Yaoguang Wei, Sheqin Dong, Xianlong Hong
    APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:406-419 [Journal]
  5. Tao Wan, Malgorzata Chrzanowska-Jeske
    A novel net-degree distribution model and its application to floorplanning benchmark generation. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:420-433 [Journal]
  6. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman
    Predictions of CMOS compatible on-chip optical interconnect. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:434-446 [Journal]
  7. João M. S. Silva, L. Miguel Silveira
    Substrate model extraction using finite differences and parallel multigrid. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:447-460 [Journal]
  8. Magdy A. El-Moursy, Eby G. Friedman
    Wire shaping of RLC interconnects. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:461-472 [Journal]
  9. Hyun-Sung Kim, Sung-Woon Lee
    LFSR multipliers over GF(2m) defined by all-one polynomial. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:473-478 [Journal]
  10. Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet
    A fast pipelined multi-mode DES architecture operating in IP representation. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:479-489 [Journal]
  11. Ming Z. Zhang, Vijayan K. Asari
    An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:490-502 [Journal]
  12. Jing Huang, Mariam Momenzadeh, Fabrizio Lombardi
    Analysis of missing and additional cell defects in sequential quantum-dot cellular automata. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:503-515 [Journal]
  13. Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
    Partitioning-based decoupling capacitor budgeting via sequence of linear programming. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:516-524 [Journal]
  14. Soumen Maity, Amiya Nayak, S. Ramsundar
    Characterization, testing and reconfiguration of faults in mesh networks. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:525-535 [Journal]
  15. Omar S. Elkeelany, Ghulam Chaudhry
    Integrating firewire peripheral interface with an ethernet custom network processor. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:536-548 [Journal]
  16. Mustafa Gök
    A novel IEEE rounding algorithm for high-speed floating-point multipliers. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:549-560 [Journal]
  17. Vishal Khandelwal, Ankur Srivastava
    Active mode leakage reduction using fine-grained forward body biasing strategy. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:561-570 [Journal]
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