Journals in DBLP

Integration
2007, volume: 40, number: 3

1. Hui Zhang, Simona Doboli, Hua Tang, Alex Doboli
   Compiled code simulation of analog and mixed-signal systems using piecewise linear modeling of nonlinear parameters: A case study for DeltaSigma modulator simulation. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:193-208 [Journal]
   
2. K. R. Santha, V. Vaidehi
   Design of efficient architectures for 1-D and 2-D DLMS adaptive filters. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:209-225 [Journal]
   
3. Jinjun Xiong, Lei He
   Full-chip multilevel routing for power and signal integrity. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:226-234 [Journal]
   
4. Sotirios G. Ziavras, Alexandros V. Gerbessiotis, Rohan Bafna
   Coprocessor design to support MPI primitives in configurable multiprocessors. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:235-252 [Journal]
   
5. Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu
   An efficient quadratic placement based on search space traversing technology. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:253-260 [Journal]
   
6. Pavel V. Nikitin, C.-J. Richard Shi
   VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:261-273 [Journal]
   
7. Kunihiro Fujiyoshi, Chikaaki Kodama, Akira Ikeda
   A fast algorithm for rectilinear block packing based on selected sequence-pair. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:274-284 [Journal]
   
8. Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
   BUSpec: A framework for generation of verification aids for standard bus protocol specifications. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:285-304 [Journal]
   
9. Jens Vygen
   New theoretical results on quadratic placement. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:305-314 [Journal]
   
10. Yiorgos Makris, Alex Orailoglu
    On the identification of modular test requirements for low cost hierarchical test path construction. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:315-325 [Journal]
    
11. Krishnan Srinivasan, Karam S. Chatha
    Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:326-354 [Journal]
    
12. Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat
    Dynamic differential self-timed logic families for robust and low-power security ICs. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:355-364 [Journal]
    
13. Sotir Ouzounov, Engel Roza, Hans Hegt, Gerard v. d. Weide, Arthur H. M. van Roermund
    Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:365-379 [Journal]