Journals in DBLP

IEEE Transactions on Reliability
2003, volume: 52, number: 4

1. Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
   Built-in redundancy analysis for memory yield improvement. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Reliability, 2003, v:52, n:4, pp:386-399 [Journal]
   
2. Fabrizio Ferrandi, Franco Fummi, Graziano Pravadelli, Donatella Sciuto
   Identification of design errors through functional testing. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Reliability, 2003, v:52, n:4, pp:400-412 [Journal]
   
3. K. Thaller, A. Steininger
   A transparent online memory test for simultaneous detection of functional faults and soft errors in memories. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Reliability, 2003, v:52, n:4, pp:413-422 [Journal]
   
4. Jun Zhao, Fred J. Meyer, Fabrizio Lombardi, Nohpill Park
   Maximal diagnosis of interconnects of random access memories. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Reliability, 2003, v:52, n:4, pp:423-434 [Journal]
   
5. J. H. Jiang, W.-B. Jone, Shih-Chieh Chang, S. Ghosh
   Embedded core test generation using broadcast test architecture and netlist scrambling. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Reliability, 2003, v:52, n:4, pp:435-443 [Journal]
   
6. W. P. M. Allen, D. G. Bailey, Serge N. Demidenko, Vincenzo Piuri
   Analysis and application of digital spectral warping in analog and mixed-signal testing. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Reliability, 2003, v:52, n:4, pp:444-457 [Journal]
   
7. Cristiana Bolchini
   A software methodology for detecting hardware faults in VLIW data paths. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Reliability, 2003, v:52, n:4, pp:458-468 [Journal]
   
8. Cecilia Metra, Luca Schiano, Michele Favalli
   Concurrent detection of power supply noise. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Reliability, 2003, v:52, n:4, pp:469-475 [Journal]
   
9. Gian-Carlo Cardarilli, A. Leandri, P. Marinucci, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
   Design of a fault tolerant solid state mass memory. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Reliability, 2003, v:52, n:4, pp:476-491 [Journal]
   
10. Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
    Designing fault-secure parallel encoders for systematic linear error correcting codes. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:492-500 [Journal]
    
11. Kaijie Wu, Ramesh Karri
    Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:501-511 [Journal]
    
12. C. Scherrer, A. Steininger
    Dealing with dormant faults in an embedded fault-tolerant computer system. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:512-522 [Journal]
    
13. A. Barros, C. Bérenguer, A. Grall
    Optimization of replacement times using imperfect monitoring information. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:523-533 [Journal]