Journals in DBLP

IEEE Trans. VLSI Syst.
2007, volume: 15, number: 1

1. Zhengtao Yu, Xun Liu
   Low-Power Rotary Clock Array Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:5-12 [Journal]
   
2. Yen-Jen Chang, Maofeng Lan
   Two New Techniques Integrated for Energy-Efficient TLB Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:13-23 [Journal]
   
3. Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
   A Test Generation Framework for Quantum Cellular Automata Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:24-36 [Journal]
   
4. Erkan Acar, Sule Ozev
   Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:37-47 [Journal]
   
5. Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
   Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:48-59 [Journal]
   
6. Dipanjan Gope, Albert E. Ruehli, Vikram Jandhyala
   Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:60-68 [Journal]
   
7. Ruibing Lu, Aiqun Cao, Cheng-Kok Koh
   SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:69-79 [Journal]
   
8. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
   A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:80-89 [Journal]
   
9. Ye Li, Bertan Bakkaloglu, Chaitali Chakrabarti
   A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:90-103 [Journal]
   
10. Zhongfeng Wang, Zhiqiang Cui
    Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:104-114 [Journal]
    
11. K. Scott Hemmert, Keith D. Underwood
    Floating-Point Divider Design for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:115-118 [Journal]
    
12. P. Rajesh Kumar, K. Sridharan
    VLSI-Efficient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:118-123 [Journal]