Journals in DBLP

IEEE Trans. VLSI Syst.
1994, volume: 2, number: 2

1. Jason Cong, Yuzheng Ding
   On area/depth trade-off in LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:137-148 [Journal]
   
2. Tassos Markas, Mark Royals, Nick Kanopoulos
   Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:149-156 [Journal]
   
3. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
   ALADIN: a multilevel testability analyzer for VLSI system design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:157-171 [Journal]
   
4. Andrew Seawright, Forrest Brewer
   Clairvoyant: a synthesis system for production-based specification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:172-185 [Journal]
   
5. K. De, C. Natarajan, D. Nair, P. Banerjee
   RSYN: a system for automated synthesis of reliable multilevel circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:186-195 [Journal]
   
6. S. C. Leung, H. F. Li
   A syntax-directed translation for the synthesis of delay-insensitive circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:196-210 [Journal]
   
7. Minjoong Rim, Ashutosh Mujumdar, Rajiv Jain, Renato De Leone
   Optimal and heuristic algorithms for solving the binding problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:211-225 [Journal]
   
8. Lishing Liu
   Partial address directory for cache access. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:226-240 [Journal]
   
9. Marc E. Levitt, Kaushik Roy, Jacob A. Abraham
   BiCMOS logic testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:241-248 [Journal]
   
10. Israel Koren, Zahava Koren, Charles H. Stapper
    A statistical study of defect maps of large area VLSI IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:249-256 [Journal]
    
11. Choong Gun Oh, Hee Yong Youn
    On concurrent error location and correction of FFT networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:257-260 [Journal]
    
12. Razak Hossain, Leszek D. Wronski, Alexander Albicki
    Low power design using double edge triggered flip-flops. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:261-265 [Journal]
    
13. Mohammad Hossain Heydari, Ioannis G. Tollis, Chunliang Xia
    Algorithms and bounds for layer assignment of MCM routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:265-270 [Journal]