Journals in DBLP

IEEE Trans. VLSI Syst.
2007, volume: 15, number: 3

1. Niraj K. Jha
   Editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:249-261 [Journal]
   
2. Alexandru Andrei, Petru Eles, Zebo Peng, Marcus T. Schmitz, Bashir M. Al-Hashimi
   Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:262-275 [Journal]
   
3. Nikhil Jayakumar, Sunil P. Khatri
   A Predictably Low-Leakage ASIC Design Style. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:276-285 [Journal]
   
4. A. Amira, S. Chandrasekaran
   Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:286-295 [Journal]
   
5. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
   Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:296-308 [Journal]
   
6. Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak
   Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:309-318 [Journal]
   
7. Ada S. Y. Poon
   An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:319-327 [Journal]
   
8. Sizhong Chen, Tong Zhang, Yan Xin
   Relaxed K-Best MIMO Signal Detector Design and VLSI Implementation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:328-337 [Journal]
   
9. Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang
   Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:338-345 [Journal]
   
10. Chen Shoushun, Amine Bermak
    Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:346-357 [Journal]
    
11. Wei-Zen Chen, Da-Shin Lin
    A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:358-365 [Journal]
    
12. Justin Gregg, Tom W. Chen
    Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:366-376 [Journal]