Journals in DBLP

IEEE Trans. VLSI Syst.
2007, volume: 15, number: 8

1. 
   Guest Editorial System-Level Interconnect Prediction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:853-854 [Journal]
   
2. Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh
   Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:855-868 [Journal]
   
3. Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
   Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:869-880 [Journal]
   
4. Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang
   Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:881-894 [Journal]
   
5. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
   Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:895-903 [Journal]
   
6. Andrew B. Kahng, Bao Liu, Qinke Wang
   Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:904-912 [Journal]
   
7. Xiaoji Ye, Frank Liu, Peng Li
   Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:913-926 [Journal]
   
8. Ian O'Connor, Faress Tissafi-Drissi, Frédéric Gaffiot, Joni Dambre, Michiel De Wilde, Jan Van Campenhout, D. Van Thourhout, Dirk Stroobandt
   Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:927-940 [Journal]
   
9. Jin Guo, Antonis Papanikolaou, H. Zhang, Francky Catthoor
   Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:941-944 [Journal]
   
10. Wenyi Feng, Jonathan W. Greene
    Post-Placement Interconnect Entropy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:945-948 [Journal]
    
11. Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow
    Routability of Network Topologies in FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:948-951 [Journal]
    
12. Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor
    Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:952-962 [Journal]
    
13. Ja Chun Ku, Yehea I. Ismail
    Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:963-970 [Journal]
    
14. A. Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
    Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:971-975 [Journal]
    
15. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Code Decompression Unit Design for VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:975-980 [Journal]