Journals in DBLP
Raghu Sastry , N. Ranganathan , Horst Bunke VLSI architectures for polygon recognition. [Citation Graph (0, 0)][DBLP ] Journal ] Anna Antola , Alberto Avai , Luca Breveglieri Modular design methodologies for image processing architectures. [Citation Graph (0, 0)][DBLP ] Journal ] Dinesh Somasekhar , V. Visvanathan A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. [Citation Graph (0, 0)][DBLP ] Journal ] Abhijit Chatterjee , Rabindra K. Roy , Manuel A. d'Abreu Greedy hardware optimization for linear digital circuits using number splitting and refactorization. [Citation Graph (0, 0)][DBLP ] Journal ] Patrick C. McGeer , Jagesh V. Sanghavi , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli ESPRESSO-SIGNATURE: a new exact minimizer for logic functions. [Citation Graph (0, 0)][DBLP ] Journal ] Vinaya Kumar Singh , A. A. Diwan A heuristic for decomposition in multilevel logic optimization. [Citation Graph (0, 0)][DBLP ] Journal ] W. K. Al-Assadi , Yashwant K. Malaiya , Anura P. Jayasumana Faulty behavior of storage elements and its effects on sequential circuits. [Citation Graph (0, 0)][DBLP ] Journal ] Soumitra Bose , Prathima Agrawal , Vishwani D. Agrawal Path delay fault simulation of sequential circuits. [Citation Graph (0, 0)][DBLP ] Journal ] Siddharth Bhingarde , Anand Panyam , Naveed A. Sherwani Middle terminal cell models for efficient over-the-cell routing in high-performance circuits. [Citation Graph (0, 0)][DBLP ] Journal ] Ed P. Huijbregts , Jochen A. G. Jess General gate array routing using a k-terminal net routing algorithm with failure prediction. [Citation Graph (0, 0)][DBLP ] Journal ] K. S. V. Gopalarao , Purnendu K. Mozumder , Duane S. Boning An integrated technology CAD system for process and device designers. [Citation Graph (0, 0)][DBLP ] Journal ] Robert Michael Owens , Thomas P. Kelliher , Mary Jane Irwin , Mohan Vishwanath , Raminder Singh Bajwa , W.-L. Yang The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. [Citation Graph (0, 0)][DBLP ] Journal ] Kaushik Roy , S. C. Prasad Circuit activity based logic synthesis for low power reliable operations. [Citation Graph (0, 0)][DBLP ] Journal ] K. De , P. Banerjee PREST: a system for logic partitioning and resynthesis for testability. [Citation Graph (0, 0)][DBLP ] Journal ] Dimitrios Kagaris , Spyros Tragoudas Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets. [Citation Graph (0, 0)][DBLP ] Journal ] D. Das , Sharad C. Seth , Vishwani D. Agrawal Accurate computation of field reject ratio based on fault latency. [Citation Graph (0, 0)][DBLP ] Journal ] D. D. Sharma , Fred J. Meyer , Dhiraj K. Pradhan Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model. [Citation Graph (0, 0)][DBLP ] Journal ] David C. Blight , Robert D. McLeod An adaptive message passing environment for water scale systems. [Citation Graph (0, 0)][DBLP ] Journal ] R. Varadarajan , F. Augustine Efficient time-space mappings of nested loops onto multidimensional systolic arrays with a flexible buffer scheme. [Citation Graph (0, 0)][DBLP ] Journal ] C. Bachelu , Martin Lefebvre A study of the use of local interconnect in CMOS leaf cell design. [Citation Graph (0, 0)][DBLP ] Journal ] C. Ying , J. Gu Automated pin grid array package routing on multilayer ceramic substrates. [Citation Graph (0, 0)][DBLP ] Journal ] 