Journals in DBLP

IEEE Trans. VLSI Syst.
1995, volume: 3, number: 2

1. Florin Balasa, Francky Catthoor, Hugo De Man
   Background memory area estimation for multidimensional signal processing systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:157-172 [Journal]
   
2. Paul E. Landman, Jan M. Rabaey
   Architectural power analysis: The dual bit type method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:173-187 [Journal]
   
3. Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal
   AVPGEN-A test generator for architecture verification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:188-200 [Journal]
   
4. R. Vemuri, R. Kalyanaraman
   Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:201-214 [Journal]
   
5. Andrés Takach, Wayne Wolf
   Scheduling constraint generation for communicating processes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:215-230 [Journal]
   
6. Brian A. A. Antao, Arthur J. Brodersen
   ARCHGEN: Automated synthesis of analog systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:231-244 [Journal]
   
7. Dan Picker, Ronald D. Fellman
   A VLSI priority packet queue with inheritance and overwrite. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:245-253 [Journal]
   
8. Hussein M. Alnuweiri, Sadiq M. Sait
   Efficient network folding techniques for routing permutations in VLSI. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:254-263 [Journal]
   
9. P. Day, J. V. Woods
   Investigation into micropipeline latch design styles. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:264-272 [Journal]
   
10. Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge
    Critical paths in circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:273-291 [Journal]
    
11. Vojin G. Oklobdzija, David Villeger
    Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:292-301 [Journal]
    
12. Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu
    A practical current sensing technique for I_DDQ testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:302-310 [Journal]
    
13. Qingjian Yu, Ernest S. Kuh
    Exact moment matching model of transmission lines and application to interconnect delay estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:311-322 [Journal]
    
14. Hyunchul Shin, Chunghee Kim
    Performance-oriented technology mapping for LUT-based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:323-327 [Journal]
    
15. Uming Ko, T. Balsara, Wai Lee
    Low-power design techniques for high-performance CMOS adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:327-333 [Journal]
    
16. Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel
    Sequential circuit testability enhancement using a nonscan approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:333-338 [Journal]
    
17. Shih-Lien Lu
    Implementation of micropipelines in enable/disable CMOS differential logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:338-341 [Journal]