The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. VLSI Syst.
1995, volume: 3, number: 3

  1. M. F. Mar, Robert W. Brodersen
    A design system for on-chip oversampling A/D interfaces. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:345-354 [Journal]
  2. Kayhan Küçükçakar, Alice C. Parker
    A methodology and design tools to support system-level VLSI design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:355-369 [Journal]
  3. Chih-Ming Chang, Shih-Lien Lu
    Design of a static MIMD data flow processor using micropipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:370-378 [Journal]
  4. Minjoong Rim, Yaw Fann, Rajiv Jain
    Global scheduling with code-motions for high-level synthesis applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:379-392 [Journal]
  5. Duen-Jeng Wang, Yu Hen Hu
    Multiprocessor implementation of real-time DSP algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:393-403 [Journal]
  6. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Power estimation methods for sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:404-416 [Journal]
  7. Brian A. A. Antao, Arthur J. Brodersen
    Behavioral simulation for analog system design verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:417-429 [Journal]
  8. Weiping Shi, W. Kent Fuchs
    Optimal interconnect diagnosis of wiring networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:430-436 [Journal]
  9. Shaahin Hessabi, M. Y. Osman, Mohamed I. Elmasry
    Differential BiCMOS logic circuits: fault characterization and design-for-testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:437-445 [Journal]
  10. Wen-Ben Jone, Paresh Gondalia, Allan Gutjahr
    Realizing a high measure of confidence for defect level analysis of random testing [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:446-450 [Journal]
  11. Uming Ko, Poras T. Balsara
    Short-circuit power driven gate sizing technique for reducing power dissipation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:450-455 [Journal]
  12. Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta
    Performance improvement technique for synchronous circuits realized as LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:455-459 [Journal]
  13. Frank Vahid, Daniel D. Gajski
    Incremental hardware estimation during hardware/software functional partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:459-464 [Journal]
  14. A. De Gloria, M. Olivieri
    Efficient semicustom micropipeline design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:464-469 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002