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Journals in DBLP

IEEE Trans. VLSI Syst.
1996, volume: 4, number: 1

  1. Herbert Dawid, Gerhard Fettweis, Heinrich Meyr
    A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:17-31 [Journal]
  2. Jeffrey C. Gealow, F. P. Herrmann, L. T. Hsu, Charles Sodini
    System design for pixel-parallel image processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:32-41 [Journal]
  3. Mani B. Srivastava, Anantha P. Chandrakasan, Robert W. Brodersen
    Predictive system shutdown and other architectural techniques for energy efficient programmable computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:42-55 [Journal]
  4. Jean Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, H. H. Touati, Philippe Boucard
    Programmable active memories: reconfigurable systems come of age. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:56-69 [Journal]
  5. Daniel D. Gajski, Sanjiv Narayan, L. Ramachandran, Frank Vahid, P. Fung
    System design methodologies: aiming at the 100 h design cycle. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:70-82 [Journal]
  6. Pao-Ann Hsiung, Sao-Jie Chen, Tsung-Chien Hu, Shih-Chiang Wang
    PSM: an object-oriented synthesis approach to multiprocessor system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:83-97 [Journal]
  7. Ti-Yen Yen, Wayne Wolf
    An efficient graph algorithm for FSM scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:98-112 [Journal]
  8. Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown
    Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:113-129 [Journal]
  9. Michele Favalli, Cecilia Metra
    Sensing circuit for on-line detection of delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:130-133 [Journal]
  10. Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor
    Finite field inversion over the dual basis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:134-137 [Journal]
  11. D. J. Kinniment
    An evaluation of asynchronous addition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:137-140 [Journal]
  12. Chin-Long Wey
    Built-in self-test (BIST) design of high-speed carry-free dividers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:141-145 [Journal]
  13. V. Chandramouli, Erik Brunvand, Kent F. Smith
    Self-Timed Design in GaAs - Case Study of a High-Speed, Parallel Multiplier. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:146- [Journal]
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